Virtex-7 -> what's the maximum frequency for LUT logic?

[ivlsi]

Hi All,

What's the maximum frequency might be achieved in Vertex-7 devices for pure logic [LUT cells]?

What's maximum frequency for Memories?

Please consider the highest grades of the devices.

Could someone provide the relevant links on Xilinx web site?

What process/technology were the Vertex-7 devices fabricated (40nm? ...)?

Thank you!

 

[pbernardi]

Virtex-7 is manufactured with 28 nm technology.

Most of question you asked can be found on Virtex-7 datasheet:

https://www.xilinx.com/support/documentation/data_sheets/ds183_Virtex_7_Data_Sheet.pdf

Some maximum frequencies for -3 speed grade:

DDR3@1866 Mb/s
IO: 533 MHz
CLB: 1818 MHz
BRAM: 601 MHz
DSP48E1: 741 MHz (all pipelines)

But keep in mind that most of this frequencies are hard to impossible to achieve in real designs.

Alco, check Virtex-7 website: https://www.xilinx.com/support/inde...supportNav/silicon_devices/fpga/virtex-7.html

 

[ivlsi]

Thanks a lot for your comments!

most of this frequencies are hard to impossible to achieve in real designs

So, what are the REAL frequencies (specially for Logic paths (between flop stages))?

Thank you!

 

[pbernardi]

Hard to say. One of these components costs some thousand of dollars... I don't have any with me, you know? :wink:

This should be carefully taken into account if you want to project with Virtex-7.

 

[ivlsi]

If I want to have a device for 500MHz CLB frequency, which one should I take?

Do Xilinx have any chart for the device selection?

What's the best way for choosing a device? Just trying to synthesize the project to various devices, see what's device it fits, then choose the speed grade, so on?

BTW, you got points from me for your helpful posts

 

[ads-ee]

If you want 500 MHz then you better be using a lot of pipelining. Typically you may see 30-40% of your setup time eating up by routing alone (based on a K7 design that I have handy). So the FF clock to out, LUT, FF setup, clock skew make up some 60-70% of the path delay.

Best thing to do is experiment a little with some typical circuits hooked together like counters, shift registers, memory, multiplexers, and build a do-nothing circuit so you can get a feel for the performance, with logic you are apt to use.

regards

 

[pbernardi]

Xilinx has comparison between components inside the same family.

Google words: "{Spartan6, Artix7, kintex7, zynq} family" should return the comparison between the components on the same family.
"{Spartan6, Artix7, kintex7, zynq} datasheet DC characteristics" should return the max. freq. speed of each component.

The max. speed depends much of what do you need, and how you will implement it. 500 MHz is not easy to reach, if you have a complex design. You can write a test code and synthesize it to have an idea.

I would recommend to have a look on Artix 7 and Kintex 7. But you told no project requirement beside speed (logic? price?)

Also, you should navigate a little across Xilinx website. There are lots of detailed and accurate information there.

 

[TrickyDicky]

So, what are the REAL frequencies (specially for Logic paths (between flop stages))?

Thank you!

It will really depend on your design. But if you're going to be pushing the limits (> 400MHz) you're going to need a max of 1 or 2 LUTs between flops, duplicated registers, extra pipeline registers just to route signals into and out of BRAMS and DSPs, and then you will need to identify false paths and multicycle paths to make life easier for the fitter.
And then you may need to start putting fit regions down to prevent the fitter spreading out logic too much.
And finally, you may need to set several different build seeds running just to get a single one to meet timing (get 20% pass rate and you'll be dead happy)

(Having spent several months trying to get a 70% full chip running at >350 MHz, I can tell you its not a fun job. The SDC file was around 1000 lines)

So, be prepared for the long haul. Get yourself a good multicore build server (or 3) to run your 10-20 nightly builds running. And make sure you have nothing planned for the next few months.

 

[FvM]

The question is a bit unclear. You are initially asking about "maximum frequency (...) for pure logic".

Later you are asking about "REAL frequencies (specially for Logic paths (between flop stages))"

In a synchronous design (FFs with logic inbetween), you don't ask for the logic switching frequency but for the propagation delay of specific logic complexity, the required setup- and hold time of the registers and the resulting maximum clock frequency. The latter will be always lower than the maximum core clock of a logic family. Because the logic complexity can be partly reduced by pipeline stages, the maximum frequency isn't fixed.