Vias between layers in CADENCE and TSMC PDK

[brayn64]

Hi,
I'm new in Cadence and I'm designing circuits with TSMC0.13um PDK. My circuit contains 8 layers, but I don't know; how to place a via between two layers? for example metal via between met1 and met2.
I'm trying to do this in schematic, may be this is not possible in the schematic? because in the vias folder of my KitDesign TSMC0.13um there are only symbolic and layout folders? if this is correct in which step, we can add vias between layers and via_gnd to take their influence in the performance of the designed circuits (during simulation with cadence).
I will appreciate your help:smile:.

 

[erikl]

I'm trying to do this in schematic, may be this is not possible in the schematic?

Right. In schematics no vias (nor layers) are used. Just wires to connect schematic symbols.

 

[brayn64]

So the vias can be placed only in the layout step (in the case CADENCE)? and their influence can be considered only in the post-layout simulation?

 

[ud23]

So the vias can be placed only in the layout step (in the case CADENCE)? and their influence can be considered only in the post-layout simulation?

yes vias can be placed in layout.yes you can simulate in the post- layout simulation.

 

[brayn64]

thanks for your help:-|