Vlsi_design_technology
Newbie level 3
Dear All,
I was doing half adder and full adder using structural modelling in VHDL. There are following warnings and errors:
(i) Instance is unbound
(ii) Possible simulation mismatch
Due to this, output shows 'U' i.e. initialized.
How can I remove it.
Thanks in advance for your time and consideration.
I was doing half adder and full adder using structural modelling in VHDL. There are following warnings and errors:
(i) Instance is unbound
(ii) Possible simulation mismatch
Due to this, output shows 'U' i.e. initialized.
How can I remove it.
Thanks in advance for your time and consideration.