I have been assigned a new project where I need to write down VHDL test bench based on the design specification and RTL code is available to me for this design.I am new to VHDL and verifaication flow. Please guide me suitable links/materials for quick start up. Thanking all of you in adavnce.
Re: VHDL & writing test bench in VHDL for RTL verifiacti
Thank You for replies. I will try to get the VHDL book. Can I get this book online? Thank You. Any good links/reading stuff for quick learning VHDL can also be helpful to me.