Actually it's not a big problem. You only need to write more codes.
if you are using a same Clk for both BRAM and UART, create a signal that is only one clk cycle high, from UART data ready.
if u r using 2 CLk's It needs some more codes.
use sBramWr for writing On BRAM
example Code for one CLK mode:
Code:
signal sUartReady :std_logic;--Slow Ready signal. UART data ready.
signal sUartReadyD1 :std_logic;
signal sBramWr :std_logic;
begin
process(CLK)
begin
if rising_edge(CLk) then
sUartReadyD1<=sUartReady;
sBramWr <=sUartReady and not (sUartReadyD1);
end if;
end process;
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