[SOLVED] VHDL Writing on BRAM from PC Serial- Clock speed mismatch

[Harish Naman]

I am currently working on image processing related work. I want to write serial data from pc to bram which i created using xillinx core generator ip. My problem is that since the speed of uart and memory are different, i am not able write the data coming from from uart to the rom. I tried using a flag variable which is raised as HIGH when the uart has received one byte and it will go LOW when the data is coming. In my BRAM write module, i am checking for the flag to be raised HIGH. Whenever the flag is raised high, i write the uart data into bram once.

But the problem is since the uart clock is slow and bram clock is fast that when the flag is raised HIGH, the program writes the uart data to memory once. But since the flag is still HIGH (due to uart speed), it writes the same uart data again.

This speed mismatch is so problematic that it writes the same uart data which was received initially to all the blocks of the RAM.

Kindly help me come out of this problem. I have search everywhere on xillinx, edaboard etc,but still can't find any sample code for above problem.
Some possible solution which i might think is:
1. using interrupt in uart (I don't know how to do it, please provide some resources)
2. using something which can detect rising edge of the flag variable so that i can store the data once every rising edge....kindly help me in this...please.

P.S. using VHDL

 

[Port Map]

Actually it's not a big problem. You only need to write more codes.
if you are using a same Clk for both BRAM and UART, create a signal that is only one clk cycle high, from UART data ready.
if u r using 2 CLk's It needs some more codes.

use sBramWr for writing On BRAM

example Code for one CLK mode:

  signal sUartReady		:std_logic;--Slow Ready signal. UART data ready.
  signal sUartReadyD1	:std_logic;
  signal sBramWr				:std_logic;
  
begin


  process(CLK)
  begin
  if rising_edge(CLk) then
	sUartReadyD1<=sUartReady;
	sBramWr      <=sUartReady and not (sUartReadyD1);
  end if;
  end process;

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[Harish Naman]

thanks a lot

Actually it's not a big problem. You only need to write more codes.
if you are using a same Clk for both BRAM and UART, create a signal that is only one clk cycle high, from UART data ready.
if u r using 2 CLk's It needs some more codes.

use sBramWr for writing On BRAM

example Code for one CLK mode:

  signal sUartReady		:std_logic;--Slow Ready signal. UART data ready.
  signal sUartReadyD1	:std_logic;
  signal sBramWr				:std_logic;
  
begin


  process(CLK)
  begin
  if rising_edge(CLk) then
	sUartReadyD1<=sUartReady;
	sBramWr      <=sUartReady and not (sUartReadyD1);
  end if;
  end process;

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