VHDL Wrapper for Verilog

[lemart92]

All - I'm trying to instantiate this Verilog block (pasted below) into my top level VHDL. I've tried to create a wrapper but I'm not having much success.

Can anyone help me out with how this is supposed to look with a VHDL wrapper around it?

Thanks!

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Code Verilog - [expand]
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`timescale 1 ps / 1 ps
module top_hw (
                input  wire         refclk_clk,                //     refclk.clk
                input  wire         reconfig_xcvr_clk,         //     refclk.clk
                input  wire         hip_serial_rx_in0,         //           .rx_in0
                output wire         hip_serial_tx_out0,        //           .tx_out0
                input  wire         local_rstn,
                output  wire        hsma_clk_out_p2,
                output  reg [3:0]   lane_active_led,
                output  reg        L0_led,
                output  reg        alive_led,
                output  reg        comp_led,
                input  wire         perstn             //  pcie_rstn.npor
        );
 
wire [31:0]  test_in;          //           .test_in
wire         fbout_reconfigclk;
 
 
  reg     [ 24: 0] alive_cnt;
  wire             any_rstn;
  reg              any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102"  */;
  reg              any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102"  */;
  wire             gen2_speed;
  wire [5:0]       ltssm;
 
assign any_rstn = perstn & local_rstn;
assign hsma_clk_out_p2 = reconfig_xcvr_clk;
assign test_in[0]    =  1'b0; // Simulation mode
assign test_in[1]    =  1'b0; // Reserved
assign test_in[2]    =  1'b0; // Reserved
assign test_in[3]    =  1'b0; // FPGA Mode
assign test_in[4]    =  1'b0; // Reserved
assign test_in[5]    =  1'b1; // Disable compliance mode
assign test_in[6]    =  1'b0; // Disable compliance mode
assign test_in[7]    =  1'b1; // Disable low power state
assign test_in[11:8] =  4'b0011;
assign test_in[31:12] =  20'h0;
 
 
  //reset Synchronizer
  always @(posedge reconfig_xcvr_clk or negedge any_rstn)
    begin
      if (any_rstn == 0)
        begin
          any_rstn_r <= 0;
          any_rstn_rr <= 0;
        end
      else
        begin
          any_rstn_r <= 1;
          any_rstn_rr <= any_rstn_r;
        end
    end
 
 
 
 
   top top (
             .pcie_cv_hip_avmm_0_refclk_clk               (refclk_clk               ),//     refclk.clk
             .clk_clk                      (reconfig_xcvr_clk        ),//     reconfig_xcvr_clk.clk
             .pcie_cv_hip_avmm_0_hip_ctrl_test_in         (test_in                  ),//           .test_in
             .pcie_cv_hip_avmm_0_hip_serial_rx_in0        (hip_serial_rx_in0        ),//           .rx_in0
             .pcie_cv_hip_avmm_0_hip_serial_tx_out0       (hip_serial_tx_out0       ),//           .tx_out0
     
             .pcie_cv_hip_avmm_0_npor_npor                (any_rstn_rr),                            //         pcie_rstn.npor
             .reset_reset_n                ((perstn==1'b0)?1'b0:(local_rstn==1'b0)?1'b0:1'b1), // reconfig_xcvr_rst.reconfig_xcvr_rst
             .pcie_cv_hip_avmm_0_npor_pin_perst           (perstn)                         //                  .pin_perst
     );
 
 
 
 
endmodule

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[ads-ee]

You should be able to instantiate it directly in the VHDL top-level without a wrapper, or you can instantiate it in a wrapper then instantiate that wrapper in the top-level (which seems a bit redundant).

input equals in : std_logic
output equals out : std_logic
output reg [3:0] should be the same as out : std_logic_vector(3 downto 0)

Here is an example of doing this.

The takeaway from that link is Verilog is case sensitive and VHDL is not so you better make sure you use the right case!

 

[FvM]

Re: VHDL wrapper for Verilog

Write a component declaration for the module and instantiate it like a VHDL entity.

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Code VHDL - [expand]
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COMPONENT top_hw 
  PORT
  (
    refclk_clk: IN STD_LOGIC;        
    reconfig_xcvr_clk: IN STD_LOGIC;
    hip_serial_rx_in0: IN STD_LOGIC;
    hip_serial_tx_out0: OUT STD_LOGIC;
    local_rstn: IN STD_LOGIC;
    hsma_clk_out_p2: OUT STD_LOGIC;
    lane_active_led: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    L0_led: OUT STD_LOGIC;
    alive_led: OUT STD_LOGIC;
    comp_led: OUT STD_LOGIC;
    perstn: IN STD_LOGIC;
  );
END COMPONENT;

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[lemart92]

Re: VHDL wrapper for Verilog

Excellent! And thanks for the link.