#### hitx

##### Member level 2

I have a problem about my codes, but I am not sure whether the problem is about while loop or not. Therefore I need someone help. My code in VHDL is as below :

if rising_edge(q) then

while i <= 3 loop

Xn := 4.0 * Xn * (1.0 - Xn) ;

y := floor (100.0 * Xn);

m <= integer ;

n := m mod 256;

result <= std_logic_vector (to_unsigned(n,8));

i := i + 1;

end loop;

end if;

In here, "q" is a clock signal having 0.75 Hz frequency. And I want to display "result" in 8 bits through leds (0-7) in FPGA board. So loop will iterate 3 times, each iteration I should observe 64,92 and 29 respectively. Now, the clock frequency is 0.75 Hz, I need to observe the numbers. However, I observed only the final value as 29 without observing 64 and 92. So in which part of the codes I missed?

Please help. Thanks.