I found a compare in old code, and I don't understand which function is used.
I can not find ">" for std_logic_vector.
VHDL has a built-in ">" for bit_vector, but it should not be used here?
I have created a small example. Look at line 21.
Tested with Modelsim 6.6d
It is possible to use the predefined relational operators on all types and arrays of all types,
if the types are the same on both sides of the operator (the array sizes can be different).
The comparison is made element by element, and if one value is left of another in the definition, it is also "less than".
For std_logic_vector, this means that 'X' is less than '0' and 'Z' is greater than '1'.