You are comparing apples to oranges here.
`include is a pre-processor command, like #include in C, which pretty much just copies and pasts the file as is into the same position where the `include exists. Its not a self contained package (as that would be a package in SV), but just a text file that makes up part of a larger text file.
VHDL has no pre-processor, so you cannot do this. But packages are self contained in VHDL, so I dont know why you would want to "include" a package inside another package, as VHDL has no include directive or keyword.
You can "use" a package almost anywhere, but all it does it make the package contents visible in the scope where it is used. so you can do this:
Code VHDL - [expand] |
1
2
3
4
5
6
| process
use std.textio.all;
begin
-- textio stuff can only be seen in here, not outside the process
end process |
But that is a question about scoping, not inclusion.
On a side note - changes to packages in VHDL 2008 allow you declare a package pretty much anywhere.
eg.
Code VHDL - [expand] |
1
2
3
4
5
6
7
8
9
10
11
12
| process
package my_package is
constant A : integer := 1;
end package;
package body my_package is
variable av : integer; -- you can put in context things - so you can put variables in packages when you declare the package where a variable can be placed
end package body my_package
begin
--do so stuff
end process; |
- - - Updated - - -
Vhdl 2008 also allows contexts, basically groups of packages that can be included in a single line:
Code VHDL - [expand] |
1
2
3
4
5
6
7
8
9
10
| context my_context is
library lib1;
use lib1.pkg.foo;
library lib2;
use lib2.pkg.bar;
end context;
--And you can just put this at the top of the file instead of all the libraries
Context lib.my_context |