process(sel1, sel2)
variable temp: std_logic_vector(1 downto 0)
begin
temp := sel1 & sel2;
case(temp)
when "10" | "11" =>
f <= '0';
when "01" =>
z <= '1';
when others =>
f <= '1';
end case
end process;
if this for FPGA/CPLD you migt need to include clock
to avoid latches
Hi,
I new that I can do it by case statement ... but what is wrong with that code by if statement..even if there is a clock or if z<='1' .. it will give the warning.
You have to mention all values of 'f' and 'z' in the code.. and also you haven't checked for sel2 in the first condition and sel1 in the 2nd.
if (sel1 = '1' AND sel2 = '0')
...
....
if (sel2 = '1' AND sel1 = '0')
If you dont explicitly mention this...then the loops can get executed when both sel1 and sel2 are '1'. So the synthesis tool will remove the second loop as it is redundant. In other words you have to check the other signals also in your IF loop.
u should either mention F and Z in each branch of your "if" statement
or have initial values for both of them and mention just the changed ones in the "if" statement branches