VHDL variable initial value problem

[hitx]

Hi dear friends,

I have a code in VHDL. Please take a look this code below.


process (clk,i)
variable xn,y : real;
begin
xn := 0.2;
if rising_edge (clk) then

i <= i + 1;
if i < 8 then
xn := 4.0 * xn * (1.0 - xn);
y := floor (100.0 * xn);
m <= (integer ) mod 256;
mem(i) <= std_logic_vector(to_unsigned(m,8));

end if;
end if;
end process;


Now, in every clk, the initial value always xn = 0.2 Is not it? But I just want it in first clk only. And I need to use variable. How can I pass that situation?

Please help..

Thanks.

 

[TrickyDicky]

why do you need to use a variable? use of a varaible often implies you're trying to do things you shouldnt for VHDL.

I take it this code is for simulation only, because real types are no appropriate for synthesis.

So, to initialise it once only, either create a reset, or initialise the variable at it's declaration:

variable xn : real := 0.2;

 

[hitx]

Hi friends,

You mean that real types are no appropriate for synthesis. Is it right even we use math_real package? Because I am using math real library for real operations. And I just get warning message when synthesis occured. By the way, is this mean that real operations in FPGA can not be applied in practical application?

And I use that code : variable xn : real := 0.2; and this time, synthesis failed. Message is "ERROR:Xst:1532 - "C:/XilinxWorks/my_PHD_prj_new/main_PHD.vhd" line 98: Real operand is not supported in this context. "

This is really confused. Your other obtion: use reset ? How should I do ?

Thanks
Bye

 

[TrickyDicky]

You cannot use real types unless they are used to setup other hardware. There is no direct translation of real types to hardware. For floating point usage, I suggest loooking into the floating point IP cores provided by Xilinx or Altera.