shaiko
Advanced Member level 5
I want to create a new VHDL type inside a package called "2d_array" .
This type will be used as an array entity intput port (or output port).
I want the port's diementions to be unconstrained in order be able to define the exact size during compilation with 2 entity generic :
"2d_array_port_depth" and "2d_array_port_width".
Is it possible with VHDL?
If yes, please show me an example.
This type will be used as an array entity intput port (or output port).
I want the port's diementions to be unconstrained in order be able to define the exact size during compilation with 2 entity generic :
"2d_array_port_depth" and "2d_array_port_width".
Is it possible with VHDL?
If yes, please show me an example.