shaiko
Advanced Member level 5
In VHDl, Is it possible to do arithmetic operations between a subtype and it's father type ?
For example:
If signals A and C are definded as integers and signal B is defined as a natural.
Is it legal to write:
C <= A + B;
For example:
If signals A and C are definded as integers and signal B is defined as a natural.
Is it legal to write:
C <= A + B;