VHDL twos complement to decimal conversion

[graphene]

I want to convert the the output I get in TWO's complement form from a ADC to decimal form before I feed it into a DAC. I am know to do that matmatically but I am unbale to frame a logic in VHDL. Can someone help me with suggestions? Is there any suggestions for such conversion functions or packages?

 

[K-J]

I want to convert the the output I get in TWO's complement form from a ADC to decimal form before I feed it into a DAC. I am know to do that matmatically but I am unbale to frame a logic in VHDL. Can someone help me with suggestions? Is there any suggestions for such conversion functions or packages?

I suggest you first post here what you say you know how to do mathematically. From there it will be critiqued. Your end state of a 'decimal form' before feeding it into a DAC doesn't make any sense.

Kevin Jennings

 

[graphene]

Sorry, I was meaning to convert that into a BINARY form instead of decimal form.

I want to know how to convert a TWO's complement into a binary form to feed to the DAC

---------------
Mathematically>>>>. check for the MSB for a ZERO or ONE to know if it is positive (MSB of 0) or negative (MSB of 1). If its negative number, complement all the bits and add one in the LSB. You get a binary value and simply with the position find their decimal representation. This is a general way to convert a twos complement to decimal.

 

[kommu4946]

Sorry, I was meaning to convert that into a BINARY form instead of decimal form.

I want to know how to convert a TWO's complement into a binary form to feed to the DAC

Lets assume that a is signed 8 bit number (which means 2's compliment ).now we want to convert it to binary representation say b is simple binary number.
signal a:signed (7 downto 0);
signal b :std_logic_vector (7 downto 0);
------

b<= std_logic_vector(a) when (a(7)='0')else std_logic_vector (not a + 1 );

dont forget to use numeric_std

 

[graphene]

thank you kommu4946... but this is what I compiled and I get wrong outputs. seems problem with my code..

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity adc_binary_converter is
	port(
		IN_TWOS_COMPLE			: in  signed (7 downto 0);
		OUT_BINARY			 	: out STD_LOGIC_VECTOR (7 downto 0)
	);
end adc_binary_converter;

architecture Behavioral of adc_binary_converter is

	signal a:signed (7 downto 0);
	signal b :std_logic_vector (7 downto 0);
	
	
begin
	a<= IN_TWOS_COMPLE;
	b<= std_logic_vector(a) when (a(7)='0')else std_logic_vector (not a + 1 );
	count_process: process (IN_TWOS_COMPLE)
	begin
		-- b<= std_logic_vector(a) when (a(7)='0')else std_logic_vector (not a + 1 );
		OUT_BINARY <= b;
	end process;
	
end Behavioral;

 

[TrickyDicky]

You are not doing binary to decimal conversion, the output is still Binary. You are taking the absolute value of the vector.

what input does the dac expect? Signed binary or offset unsigned binary?

 

[graphene]

in my first post where i had asked for a decimal conversion was wrong... i need a two's complement to binary conversion... in real, my adc gives twos complement output which is input to my fpga and the fpga should be programmed to provide binary output to the dac. this is where I am struggling

 

[ads-ee]

I noticed your process is sensitive to IN_TWOS_COMP and not b, which is what is used in the assignment to OUT_BINARY.

Not sure why you don't just use IN_TWOS_COMP and the equation in the process directly and assign all that to OUT_BINARY.

 

[axcdd]

as kommu4946 said
b<= std_logic_vector(a) when (a(7)='0')else std_logic_vector (not a + 1 );
or just
b <= std_logic_vector(abs(a));

remember that your MSB will be always 0 so your DAC will work 3dB under FS.

 

[ads-ee]

I really think the OP would want offset binary from the 2c conversion. As axcdd points out what is being done is an absolute value function.

I would think something like

OUT_OFFSET_BINARY <= std_logic_vector(IN_TWOS_COMP+2**7);

to produce the offset binary for the DAC.

 

[graphene]

@kommu4946 .... thank you once again...
@ads-ee... thank you .I understood my issue in adding to sensitivity list...
@axcdd... using abs also works... thank you..

- - - Updated - - -

@ads-ee Can you please tell me what this OFFSET_BINARY to be given to the DAC. I did not understand the necessity for that.

 

[ads-ee]

Suppose the signal looks like this triangle wave from ADC having a 4-bit output.

[FONT=Fixedsys]+7 ______
        /\      /\      /\   
 0 ___ /  \    /  \    /  \  
      /    \  /    \  /    \ 
-7 __/      \/      \/      \[/FONT]

Will end up being the following if you use the absolute value:

[FONT=Fixedsys]+7 __    
     \  /\  /\  /\  /\  /\  /
 0 __ \/  \/  \/  \/  \/  \/ 
[/FONT]

And if you use offset binary:

[FONT=Fixedsys]+15 ______
         /\      /\      /\   
 +8 ___ /  \    /  \    /  \  
       /    \  /    \  /    \ 
  0 __/      \/      \/      \
[/FONT]

The result is the input to the DAC is an offset binary value that has an output that looks just like the ADC signal otherwise you end up with a signal that is of higher frequency due to the folding of the negative values into the positive range.

Regards

 

[graphene]

@ads-ee: wonderful... never though about it... thank you a lot mate.