[SOLVED] VHDL to Verilog: Mixed edge- and level-sensitive signals?

[Artlav]

Hello.
Trying to get a mixed VHDL/Verilog project to a common denominator, specifically Verilog.
But there is a piece that i don't know how to translate.

VHDL original:

process (cnt) is
begin
 if (cnt = "0000") then 
  stop <= '1';
 else
  stop <= '0';
 end if;
end process;

process (rst,stop,c[10]) is
begin
 if (rst='0') then
  cnt <= "0001";
 elsif ((rising_edge(c[10])) and (stop='0'))  then
  cnt <= cnt + 1;
 end if;
end process;

This compiles fine and without warnings.


First attempt, translated as written.
Getting "Unexpected event in always block sensitivity list" error for the second "always".
Apparently, you can not put edge and level sensitive signals in one always block.

always @(cnt)
begin
 if (cnt==4'b0000) begin
  stop <= 1'b1;
 end else begin
  stop <= 1'b0;
 end
end

always @(rst or stop or posedge c[10])
begin
 if (!rst) begin
  cnt <= 4'b0001;
 end else if (c[10] && !stop) begin
  cnt <= cnt + 1'b1;
 end
end

Second attempt, tried to start to work around it, but now i get "Found 4-bit latch for signal <cnt>." warnings.

always @(rst or stop or c[10])
...

Trying to resolve the latch by adding a last else produce lots of "the following signal(s) form a combinatorial loop" warnings.
Which is kind of the point, but didn't happen in the VHDL case.

In any case, i still have no idea how to do the rising edge trigger properly here, and i'm not familiar enough with the design to reimplement it by the meaning.
So, can anyone help to translate this part correctly?

- - - Updated - - -

Resolved the problem like so:

always @(negedge rst or posedge c[10])
begin
 if (!rst) begin
  cnt <= 4'b0001;
 end else if (!stop) begin
  cnt <= cnt + 1'b1;
 end
end

Sorry for the bother.

 

[shaiko]

Other than the "translation" issue, there're other improper things with your code.

process (rst,stop,c[10]) is
begin
 if (rst='0') then
  cnt <= "0001";
 elsif ((rising_edge(c[10])) and (stop='0'))  then
  cnt <= cnt + 1;
 end if;
end process;

A synchronous process (one that uses flip flops) shall be sensitive to the system clock and to an asynchronous reset (if such exists) - and to them only!

Is "c[10]" the clock of your design ?

 

[permute]

As mentioned, this code would be more familiar if the "if stop == 0" was within the "if rising_edge(clk)" block.

 

[FvM]

The problem is brought up by the different Verilog and VHDL semantic for edge sensitive events.

Als already meantioned, the signal stop should not appear in the VHDL process sensitivity list, but it doesn't hurt. When synthesizing VHDL, sensitivity lists are effectively ignored by the design compiler.

Likewise you can't rely on sensitivity list when translating VHDL to Verilog.

Verilog has a strict template for synthesizable synchronous registers with additional asynchronous inputs, you finally applied it in the last code variant.

Translating VHDL to Verilog doesn't work word-by-word. You must understand the meaning of the VHDL code and know the required Verilog syntax.