VHDL to VERILOG CONVERTION

conv_std_logic_vector verilog

Hi Guys,

I need to convert this VHDL code into the Verilog. I tried it with the online free converter software, the end result still have errors, can please advice over here?

VHDL CODE as followed
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

-----------------------------ENTITY DECLARATION--------------------------------

entity comb_divider is

generic (DWIDTH : integer := 8);

port (dvdnd_i : in std_logic_vector(DWIDTH-1 downto 0); -- Dividend
dvsor_i : in std_logic_vector(DWIDTH-1 downto 0); -- Divisor
qutnt_o : out std_logic_vector(DWIDTH-1 downto 0); -- Quotient
rmndr_o : out std_logic_vector(DWIDTH-1 downto 0)); -- Remainder

end comb_divider;


architecture rtl of comb_divider is

begin -- rtl

p_divide: process (dvdnd_i, dvsor_i)

variable v_actl_dvdnd : unsigned(DWIDTH-1 downto 0);
variable v_dffrnc : unsigned(DWIDTH-1 downto 0);
variable v_qutnt : unsigned(DWIDTH-1 downto 0);

begin -- process p_divide

v_actl_dvdnd := unsigned(dvdnd_i);

for i in DWIDTH-1 downto 0 loop
if conv_std_logic_vector(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH) >=
dvsor_i then
-- Divisor can be subtracted
v_qutnt(i) := '1';
v_dffrnc := conv_unsigned(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH)
- unsigned(dvsor_i);
if i /= 0 then
v_actl_dvdnd(DWIDTH-1 downto i) := v_dffrnc(DWIDTH-1-i downto 0);
v_actl_dvdnd(i-1) := dvdnd_i(i-1);
end if;
else
v_qutnt(i) := '0';
v_dffrnc := conv_unsigned(v_actl_dvdnd(DWIDTH-1 downto i),DWIDTH);
end if;
end loop; -- i

rmndr_o <= std_logic_vector(v_dffrnc);
qutnt_o <= std_logic_vector(v_qutnt);

end process p_divide;

end rtl;

VERILOG CODE as followed
module comb_divider (
dvdnd_i,
dvsor_i,
qutnt_o,
rmndr_o);

parameter DWIDTH = 8;

input [DWIDTH - 1:0] dvdnd_i;
input [DWIDTH - 1:0] dvsor_i;
output [DWIDTH - 1:0] qutnt_o;
output [DWIDTH - 1:0] rmndr_o;

reg [DWIDTH - 1:0] qutnt_o;
reg [DWIDTH - 1:0] rmndr_o;
reg [DWIDTH - 1:0] p_divide_v_actl_dvdnd;
reg [DWIDTH - 1:0] p_divide_v_dffrnc;
reg [DWIDTH - 1:0] p_divide_v_qutnt;

// process p_divide
integer V2V_i;


always @(dvdnd_i or dvsor_i)
begin : p_divide
p_divide_v_actl_dvdnd = dvdnd_i;
for (V2V_i = DWIDTH - 1; V2V_i >= 0; V2V_i = V2V_i - 1)
begin
if (p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i] >= dvsor_i)
begin
p_divide_v_qutnt[V2V_i] = 1'b 1;
p_divide_v_dffrnc = p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i] - dvsor_i;
if (V2V_i !== 0)
begin
p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i] = p_divide_v_dffrnc[DWIDTH - 1 - V2V_i:0];
p_divide_v_actl_dvdnd[V2V_i - 1] = dvdnd_i[V2V_i - 1];
end
end
else
begin
p_divide_v_qutnt[V2V_i] = 1'b 0;
p_divide_v_dffrnc = p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i];
end
end
rmndr_o <= p_divide_v_dffrnc;
qutnt_o <= p_divide_v_qutnt;
end
endmodule // module comb_divider

The verilog compiler complain that the bit width must be constant.
Errors : p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i] = p_divide_v_dffrnc[DWIDTH - 1 - V2V_i:0];
I tried with NCVERILOG and MODELSIM compiler both fail me the same problems, please advice anyway to fix this convertion problem.

connect verilog reg to std_logic_vector

p_divide_v_actl_dvdnd[DWIDTH - 1:V2V_i] = p_divide_v_dffrnc[DWIDTH - 1 - V2V_i:0];

I think you should use a decode for all the bits of p_divide_v_actl_dcdnd to select to connect each bit of p_divide_v_diffrnc.

Ryan

from vhdl to verilog free converter

Compile your VHDL code with Design Compiler and convert it into VHDL gate level design, unparameterized the parameters by [-param] option during elaboration, and finally rewrite the code in Verilog by issueing the instruction Write -format Verilog ...