VHDL To nVerilog Conversion

Hi

Can Anybody please help in decoding the functionality of

following VHDL functions i.e what are they trying to do as i am newbie in VHDL and is there any verilog equivalent code possible for these functions

type char_array_t is array (natural range <>) of character;
type char_file_t is file of character;
type array_file_struct_t is array (natural range <>) of file_struct_t;


type file_struct_t is record
width : integer; --number of bits
hexa : boolean; --HEXA or not
sign : boolean; --signed or not
padbin: natural; --binary file option : number of bits of padding for this component
end record file_struct_t;



function concatenate_file_struct(x:array_file_struct_t) return array_file_struct_t is
alias x_value : array_file_struct_t(x'length-1 downto 0) is x;
begin
return x_value;
end function concatenate_file_struct;


-
procedure my_file_write(bf : inout bitfile_struct_t; bits : in character; numbits : in integer; char_file_t : in character ) is --file type replaced by in as tol does not supports corresponding conversion
variable bits_vector : std_logic_vector(7 downto 0);
variable char : character;
begin
bits_vector := uint2vect(character'pos(bits),8);
bf.state := bf.state or (vector_sll(bits_vector,bf.statebits));
bf.totalbits := bf.totalbits+numbits;
if bf.statebits + numbits >= 8 then
char := character'val(vect2uint(bf.state));
write(f,char);
bf.state := vector_srl(bits_vector,8-bf.statebits);
bf.statebits := numbits+bf.statebits-8;
else
bf.statebits := bf.statebits+numbits;
end if;
end procedure my_file_write;