VHDL testbench read stimulus from file

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--LOADING DATA FROM FILE-----------
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type signal_storage is array (integer range <>)of std_logic_vector (data_width-1 downto 0);
signal mem : signal_storage (0 to data_storage-1);
   
        procedure Load_ROM (signal data_word :inout signal_storage) is
        -- Open File in Read Mode
        file romfile   :text open read_mode is "signal_record.txt";
        variable lbuf  :line;
        variable i     :integer := 0;
        variable fdata :std_logic_vector (data_width-1 downto 0);
        begin
         while not endfile(romfile) loop
            -- read digital data from input file
             readline(romfile, lbuf);
             read(lbuf, fdata);
             data_word(i) <= fdata;
             i := i+1;
         end loop;
        end procedure;

address_count :process(i_clk, i_read_en)
   begin
        if rising_edge(i_clk) then
         if i_read_en = '1' then
          r_reg <= r_next;
         end if;
        end if;
end process;

r_next <= (others=>'0') when r_reg = (samples-1) else r_reg + 1;

stim_proc: process
   begin         
        wait for 100 ns;
        i_arst <='1';
        wait for 300 ns;
        i_arst <='0';
        wait for 1000 ns;
        i_read_en <='1';
        i_data <= mem(to_integer(r_reg));
        wait for 6000 ns;
        i_read_en <='0';
        wait;
        assert false report "simulation ended" severity failure;
end process;

i_read_en <='1';
i_data <= mem(to_integer(r_reg));
wait for 6000 ns;