VHDL Testbench getting (U) in simulation waveform result

entity full_adder is
    Port ( A : in STD_LOGIC;
       B : in STD_LOGIC;
       Cin : in STD_LOGIC;
       S : out STD_LOGIC;
       Cout : out STD_LOGIC);
  end full_adder;

  architecture Behavioral of full_adder is

  begin
   S<=A xor B xor Cin;
   Cout<=(A and B)or(B and Cin)or(A and Cin);

   end Behavioral;

 entity full_adder_2bit is
    Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
       B : in STD_LOGIC_VECTOR (1 downto 0);
       Cin : in STD_LOGIC;
       S : out STD_LOGIC_VECTOR (1 downto 0);
       Cout : out STD_LOGIC);
end full_adder_2bit;


architecture Behavioral of full_adder_2bit is
Component full_adder
port(A : in STD_LOGIC;
       B : in STD_LOGIC;
       Cin : in STD_LOGIC;
       S : out STD_LOGIC;
        Cout : out STD_LOGIC);  
end component;
signal C:STD_LOGIC;   
begin
Bit_adder0: full_adder port map(A=>A(0),
                    B=>B(0),
                    Cin=>Cin,
                    S=>S(0),
                    Cout=>C);
 Bit_adder1:full_adder port map(A=>A(1),
                           B=>B(1),
                           Cin=>C,
                            S=>S(1),
                            Cout=>Cout);

 end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity full_adder_2bit_tb is  
--  Port ( );
end full_adder_2bit_tb;

architecture Behavioral of full_adder_2bit_tb is
component full_adder_2bit 
port( A : in STD_LOGIC_VECTOR (1 downto 0);
      B : in STD_LOGIC_VECTOR (1 downto 0);
      Cin : in STD_LOGIC;
      S : out STD_LOGIC_VECTOR (1 downto 0);
      Cout : out STD_LOGIC);
end component; 
constant Period: Time :=10ns;
signal A_tb: STD_LOGIC_VECTOR(1 downto 0):= (others=>'0');
signal B_tb:STD_LOGIC_VECTOR(1 downto 0):= (others => '0');
signal Cin_tb:STD_LOGIC;
signal S_tb: STD_LOGIC_VECTOR(1 downto 0);
signal Cout_tb:STD_LOGIC;

begin
Bit_adder_tb0: full_adder_2bit port map
(A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb);

stim_proc: process
variable i,j :integer;
begin
for Cin in 0 to 1 loop
 for i in 0 to 2 loop
  for j in 0 to 2 loop
 A_tb <=STD_LOGIC_VECTOR( to_unsigned(i,2)); 
B_tb <= STD_LOGIC_VECTOR(to_unsigned(j,2));
    wait for period;
end loop
end loop
end loop
wait;
end process;
end Behavioral;

signal Cin_tb:STD_LOGIC:='0';

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity full_adder_2bit_tb is  
--  Port ( );
end full_adder_2bit_tb;

architecture Behavioral of full_adder_2bit_tb is
component full_adder_2bit 
port( A : in STD_LOGIC_VECTOR (1 downto 0);
      B : in STD_LOGIC_VECTOR (1 downto 0);
      Cin : in STD_LOGIC;
      S : out STD_LOGIC_VECTOR (1 downto 0);
      Cout : out STD_LOGIC);
end component; 
constant Period: Time :=10ns;
signal A_tb: STD_LOGIC_VECTOR(1 downto 0):= (others=>'0');
signal B_tb:STD_LOGIC_VECTOR(1 downto 0):= (others => '0');
[B]signal Cin_tb:STD_LOGIC:='0';[/B]
signal S_tb: STD_LOGIC_VECTOR(1 downto 0);
signal Cout_tb:STD_LOGIC;

begin
Bit_adder_tb0: full_adder_2bit port map
(A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb);

stim_proc: process
variable i,j :integer;
begin
[B]for C in 0 to 1 loop
    Cin_tb<=STD_LOGIC(to_unsigned(C,1));[/B] 
for i in 0 to 2 loop
  for j in 0 to 2 loop
 A_tb <=STD_LOGIC_VECTOR( to_unsigned(i,2)); 
B_tb <= STD_LOGIC_VECTOR(to_unsigned(j,2));
    wait for period;
end loop
end loop
end loop
wait;
end process;
end Behavioral;