omara007
Advanced Member level 4
- Joined
- Jan 6, 2003
- Messages
- 1,237
- Helped
- 50
- Reputation
- 102
- Reaction score
- 16
- Trophy points
- 1,318
- Location
- Cairo/Egypt
- Activity points
- 9,716
Hi folks
Is there any VHDL template or coding guidelines suggested by Xilinx to infer its Distributed RAM the same way they suggest some other templates for Block RAM inference ?
P.S. I don't want to use CoreGen as I want to keep everything in my VHDL code.
My device is Spartan-3A DSP
Is there any VHDL template or coding guidelines suggested by Xilinx to infer its Distributed RAM the same way they suggest some other templates for Block RAM inference ?
P.S. I don't want to use CoreGen as I want to keep everything in my VHDL code.
My device is Spartan-3A DSP