VHDL synthesize error...

I compiled my code in model sim .it works perfect.but wen i synthesize it to Design Vision tool .It give error and warrning like
Warning: /home/eselab010/ex9/datapath.vhd:51: Initial values for signals/variables are not supported for synthesis by default. They are ignored. (VHD-7)
Warning: /home/eselab010/ex9/datapath.vhd:61: Potential simulation-synthesis mismatch if index exceeds size of array 'a'. (ELAB-349)
Error: /home/eselab010/ex9/datapath.vhd:67: Constant value required. (ELAB-922)

my code is given below :

library IEEE;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_1164.all;



entity ADDSHIFT_BEH is
generic(m: integer :=4; n: integer := 4 );
PORT(
--EN_LOAD:in BIT;
EN_ADD:in BIT;
EN_SHIFT:in BIT;
EN_COUNT : in BIT ;
--EN_COUNT: in BIT;
a :in unsigned( n-1 downto 0);-- :="0000";
b: in unsigned(m-1 downto 0) ;--:= "0000";
c: out unsigned(m+n-1 downto 0);
CLK : in bit;
RESET_N : in bit
);
end;


architecture DATAPATH_BEH of ADDSHIFT_BEH is


signal p: unsigned(m+n-1 downto 0); --:= (others=>'0');
signal temp: unsigned(m+n-2 downto 0);-- := (others =>'0');

signal COUNT: INTEGER;


begin


ADDrocess(CLK, RESET_N)
begin

if RESET_N = '0' then
p <= (others =>'0');
--elsif CLK = '1' then
elsif CLK'EVENT and CLK = '1' then
if EN_ADD= '1' then
p<=p+temp;
end if;
end if;
c<= p;
end process;

SHIFTrocess(CLK, RESET_N)--,p)
variable j: integer :=0;

begin

if RESET_N = '0' then
temp <= (others =>'0');
elsif CLK'EVENT and CLK = '1' then
if EN_SHIFT='1' then

if a(COUNT)='1'then
if COUNT=0 then
temp <= temp+b;
else
temp <= (others =>'0');
temp <= temp+b;
loop2: for j in 0 to COUNT loop
temp <= temp((temp'left-1) downto 0) & "0";
end loop loop2;

end if;
end if;
end if;

end if;
end process;






COUNTERrocess(CLK, RESET_N)
begin
if RESET_N = '0' then
count<= 0;
elsif CLK'EVENT and CLK = '1' then
if EN_COUNT='1' then
count<=count+1;
else
count<=count;
end if;
end if;
end process;

end DATAPATH_BEH;

--end if;