Re: vhdl synthesizable codes for fast adders and fast multip
I think, the question title is misleading. This is no VHDL problem. You have to refer to the low level hardware primitives of the respective FPGA family. The vendor usually has examples how to utilize them in a VHDL design, like the Altera "Synthesis Cookbook".
But in most the cases, the synthesis tool can be expected to generate almost optimal gate level logic from behavioural code, as already mentioned.