VHDL syntax for a loop

[Binome]

Hi,
I've noticed the "for...generate" statement need a "begin" but my designs work without it.
What is the difference?
Thanks.

 

[TrickyDicky]

adding the begin allows you to declare signals local to that loop iteration:

some_gen : for i in 0 to N generate
  signal internal : std_logic;
begin

  internal <= ip(i) and enable;

  inst : my_entity
  port map (
    enable => internal
  );

 

[Binome]

OK
Thanks.