Dec 8, 2013 #1 V Vidya Kumar Newbie level 3 Joined Dec 5, 2013 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Location Abu Dhabi Activity points 22 Can i do assignments like: a[2]<=b[2]??? When I had made this statement i got VHDL syntax error:signature must have ']', but found <decimal_literal> 2 instead What changes need to be done for this statement??
Can i do assignments like: a[2]<=b[2]??? When I had made this statement i got VHDL syntax error:signature must have ']', but found <decimal_literal> 2 instead What changes need to be done for this statement??
Dec 8, 2013 #2 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 How are 'a' and 'b' defined?
Dec 8, 2013 #3 S SynthWorks Member level 2 Joined Jun 4, 2013 Messages 42 Helped 18 Reputation 36 Reaction score 21 Trophy points 1,288 Activity points 1,712 You need parentheses not square brackets: a(2)<=b(2) ;