VHDL syntax error........

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Vidya Kumar

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Can i do assignments like:
a[2]<=b[2]???
When I had made this statement i got
VHDL syntax error:signature must have ']', but found <decimal_literal> 2 instead
What changes need to be done for this statement??
 

How are 'a' and 'b' defined?
 

You need parentheses not square brackets:
a(2)<=b(2) ;
 

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