VHDL syntax error........

[Vidya Kumar]

Can i do assignments like:
a[2]<=b[2]???
When I had made this statement i got
VHDL syntax error:signature must have ']', but found <decimal_literal> 2 instead
What changes need to be done for this statement??

 

[shaiko]

How are 'a' and 'b' defined?

 

[SynthWorks]

You need parentheses not square brackets:
a(2)<=b(2) ;