VHDL SINE LUT using type "real"

library ieee ;
	use ieee.std_logic_1164.all ;
	use ieee.numeric_std.all ;
	use ieee.math_real.all ;
 
entity sine_lut is

generic
(
    WIDTH_FRACTION_ANGLE    : natural := 4  ; -- 4 gives us a resolution of 1/16
    WIDTH_FRACTION_RESULT   : natural := 10 
) ;

port 
(
	IN_CLOCK    :   in  std_logic                                                   ;																		    
	IN_ANGLE    :   in  std_logic_vector ( 7 + WIDTH_FRACTION_ANGLE - 1 downto 0 )  ;   -- 90 is 1011010 ( 7 bits ). A sign bit isn't needed ( the user shall exploit the sine symmetry ).	     
            
	OUT_RESULT  :   out std_logic_vector ( WIDTH_FRACTION_RESULT downto 0 )             -- One integer bit + WIDTH_FRACTION_RESULT
) ; 
    
end entity sine_lut ;

architecture rtl_sine_lut of sine_lut is 

type type_lut_sine_real     is array ( 0 to 2 ** ( IN_ANGLE ' length ) - 1 ) of real ;
type type_lut_sine_slv      is array ( 0 to 2 ** ( IN_ANGLE ' length ) - 1 ) of std_logic_vector ( OUT_RESULT ' range ) ;

[COLOR="#FF0000"]signal lut_sine_real    : type_lut_sine_real ;
signal lut_sine_slv     : type_lut_sine_slv ;[/COLOR]

begin 

    generate_sine_lut : for index in 0 to 2 ** ( IN_ANGLE ' length ) - 1
    generate 
                
        lut_sine_real ( index ) <= sin ( real ( index ) * ( MATH_PI / 180.0 ) / ( real ( 2 ** WIDTH_FRACTION_ANGLE ) ) ) ;  -- Multiplying by ( MATH_PI / 180.0 ) converts from degrees to radians. 
        lut_sine_slv ( index )  <= std_logic_vector ( to_unsigned ( integer ( lut_sine_real ( index ) * ( real ( 2 ** WIDTH_FRACTION_RESULT ) ) ) , OUT_RESULT ' length ) ) ;  
    
    end generate ;

    reading_from_memory : process ( IN_CLOCK ) is
    begin 
        if rising_edge ( IN_CLOCK ) then 
            OUT_RESULT <= lut_sine_slv ( to_integer ( unsigned ( IN_ANGLE ) ) ) ;
        end if ;
    end process reading_from_memory ;
 
end architecture rtl_sine_lut ;