Wow, let me get my crystal ball....Oops, I dropped it and it broke, so you'll have to post your code and how you run the simulation.
Gee, reread your post and think about, how is anyone going to help me with only vague/useless information?
Ads-ee I sympathise where you're coming from.
Msakarim, are you using writeline or write? Is it being loop'd successfully?
Pls post code
ENTITY mem_tb IS
END mem_tb;
ARCHITECTURE behavior OF mem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mem
PORT(
clk : IN bit;
rst : IN bit;
write1 : IN bit;
datai : IN integer range 0 to 255;
address : IN bit_vector(12 downto 0);
datao : OUT integer range 0 to 255
);
END COMPONENT;
--Inputs
signal clk : bit := '0';
signal rst : bit := '0';
signal write1 : bit := '0';
signal datai : integer range 0 to 255 :=0;
signal address :bit_vector(12 downto 0) := (others => '0');
--Outputs
signal datao : integer range 0 to 255;
file file_i : text;
file file_o : text;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mem PORT MAP (
clk => clk,
rst => rst,
write1 => write1,
datai => datai,
address => address,
datao => datao
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable v_ILINE : line;
variable v_OLINE : line;
variable datain: integer range 0 to 255;
begin
file_open(file_i, "C:\Users\hp\Documents\Desktop\Lena.txt", read_mode);
file_open(file_o, "C:\Users\hp\Documents\Desktop\Lena2.txt", write_mode);
while not endfile(file_i) loop
readline(file_i, v_ILINE);
read(v_ILINE, datain);
datai<=datain;
wait for 60 ns;
write(v_OLINE, datao);
writeline(file_o, v_OLINE);
end loop;
file_close(file_i);
file_close(file_o);
wait;
end process;
END;
The output is only written every 60 ns. How long do you run the simulation for?
The output is only written every 60 ns. How long do you run the simulation for?
No it's not, I'm assuming the write1 is active high, which means the tb never writes to the ram. I'm assuming rst is active high also, because if it isn't then the ram is in permanent reset.
I have no clue where this mem component came from as I've never seen bit and bit_vector used in synthesizable code. This would require conversions in a world full of std_ulogic* and std_logic* code.
Basically without further information we can't make any determination of the functionality or lack thereof of this undocumented code.
entity mem is
port
(clk,rst,write1: in bit;
datai:in integer range 0 to 255;
address :in bit_vector (12 downto 0);
datao: out integer range 0 to 255);
end mem;
------------------------------------------------architecture---------------------
architecture behavioral of mem is
type rom_type is array (0 to 65535) of integer range 0 to 255;
signal rom: rom_type ;
begin
process(clk,write1)
begin
IF(CLK'EVENT AND CLK='1') THEN
if(write1 = '1')then
rom(to_integer(unsigned(address)))<=datai;
else
datao<=rom(to_integer(unsigned(address)));
end if;
end if;
end process;
end behavioral;
IF(CLK'EVENT AND CLK='1') THEN
if(write1 = '1')then
signal write1 : bit := '0';
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 write1 <= '1' after 200 ns; -- you should probably modify this line and do this when you have new input data. process (clk) begin if rising_edge(clk) then if (write1 = '1') then address <= address + 1; -- you figure out the bit_vector conversions to make this work -- you need to be more careful what types you use. end if; end if; end
In your simulation results, the clk signal is not toggling. Make sure that the clk is toggling.
Rom " just a name " :smile:
Ok, i'll try it now
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