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VHDL Simulation problem

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MSAKARIM

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I want to write output of .vhd file to text file ,I know the syntax and i really do it but during simulation only one line of text file is written at each" run" and data to be written is too much ,this takes more time and effort !
is there any method to write all lines of text file with one "run" ?
by the way i'm using "modelsim"
 

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Wow, let me get my crystal ball....Oops, I dropped it and it broke, so you'll have to post your code and how you run the simulation.



Gee, reread your post and think about, how is anyone going to help me with only vague/useless information?
 

wtr

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Wow, let me get my crystal ball....Oops, I dropped it and it broke, so you'll have to post your code and how you run the simulation.



Gee, reread your post and think about, how is anyone going to help me with only vague/useless information?

Ads-ee I sympathise where you're coming from.

Msakarim, are you using writeline or write? Is it being loop'd successfully?
Pls post code
 

MSAKARIM

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Ads-ee I sympathise where you're coming from.

Msakarim, are you using writeline or write? Is it being loop'd successfully?
Pls post code


Code:
ENTITY mem_tb IS
END mem_tb;
 
ARCHITECTURE behavior OF mem_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT mem
    PORT(
         clk : IN  bit;
         rst : IN  bit;
         write1 : IN  bit;
         datai : IN  integer range 0 to 255;
         address : IN  bit_vector(12 downto 0);
         datao : OUT  integer range 0 to 255
        );
    END COMPONENT;
	

   --Inputs
   signal clk : bit := '0';
   signal rst : bit := '0';
   signal write1 : bit := '0';
   signal datai : integer range 0 to 255 :=0;
   signal address :bit_vector(12 downto 0) := (others => '0');

 	--Outputs
   signal datao : integer range 0 to 255;

    file file_i : text;
  file file_o : text;
    


  -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: mem PORT MAP (
          clk => clk,
          rst => rst,
          write1 => write1,
          datai => datai,
          address => address,
          datao => datao
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
	variable v_ILINE     : line;
    variable v_OLINE     : line;
	variable datain: integer range 0 to 255;
	
   begin	
file_open(file_i, "C:\Users\hp\Documents\Desktop\Lena.txt", read_mode);
    file_open(file_o, "C:\Users\hp\Documents\Desktop\Lena2.txt", write_mode);
	  while not endfile(file_i) loop
      readline(file_i, v_ILINE);
      read(v_ILINE, datain);
    datai<=datain;
	
    

      wait for 60 ns;
		write(v_OLINE, datao);
      writeline(file_o, v_OLINE);
    end loop;
 
    file_close(file_i);
    file_close(file_o);
     
    wait;
		
		
   end process;

END;
 

TrickyDicky

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The output is only written every 60 ns. How long do you run the simulation for?
 

K-J

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The output is only written every 60 ns. How long do you run the simulation for?

And more to the point, why is there a 'wait for 60 ns' inside the loop that reads and writes anyway? The input file won't change since it is opened to read and should be locked by the OS.

Kevin Jennings
 

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I noticed you don't have any code to address, write, or reset the RAM so I'm not sure what you are expecting to read from the RAM and output to a file, as it is currently written you will only see one value, i.e. the initial value of datao written to the output file every 60 ns as datao never gets updated.
 

MSAKARIM

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The output is only written every 60 ns. How long do you run the simulation for?

Just try with 60 s but useless!
file input has 65335 line , also file output should have the same number of lines

I explain for you what i want exactly :
this code is a test bench for ram , i want to store data of txt file input in ram , then out this data from ram to other txt file
 

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You need to post the simulation results you are seeing, as we can't help without seeing what you are seeing. Besides that the mem module is not posted so I wrote one, but I don't know if it is the same as what you are using so what I wrote in post #7 might be incorrect depending on what your mem module does. As it is the code will write every 60 ns to the output file, but with the exact same initial value of datao forever as there is nothing being written or read from the RAM to update the output datao.

In the future when asking a question always supply too much information with the expectation that others don't have any clue what you are doing and how you are doing it. Don't expect useful answers until you give enough information so we can understand what you are observing, because we aren't standing over your shoulder watching you work!
 

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Your code isnt really writing the data to ram. It's just writing it to address 0 in the ram, and then back out again.
 

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No it's not, I'm assuming the write1 is active high, which means the tb never writes to the ram. I'm assuming rst is active high also, because if it isn't then the ram is in permanent reset.

I have no clue where this mem component came from as I've never seen bit and bit_vector used in synthesizable code. This would require conversions in a world full of std_ulogic* and std_logic* code.

Basically without further information we can't make any determination of the functionality or lack thereof of this undocumented code.
 

MSAKARIM

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No it's not, I'm assuming the write1 is active high, which means the tb never writes to the ram. I'm assuming rst is active high also, because if it isn't then the ram is in permanent reset.

I have no clue where this mem component came from as I've never seen bit and bit_vector used in synthesizable code. This would require conversions in a world full of std_ulogic* and std_logic* code.

Basically without further information we can't make any determination of the functionality or lack thereof of this undocumented code.


Firstly , thank you all for your replies and notes and i'm sorry if my question not clear

code of mem :
Code:
entity mem is
port
(clk,rst,write1: in bit;
datai:in integer range 0 to 255;
address :in bit_vector (12 downto 0);
datao: out integer range 0 to 255);
end mem;
------------------------------------------------architecture---------------------
architecture behavioral of mem is
  
	  
	
   
type rom_type is array (0 to 65535) of  integer range 0 to 255;




 signal rom: rom_type ;

begin



process(clk,write1)
   
    begin
IF(CLK'EVENT AND CLK='1') THEN 
if(write1 = '1')then
    
      rom(to_integer(unsigned(address)))<=datai;
        
else 
datao<=rom(to_integer(unsigned(address)));

end if;
end if;
end process;
    
end behavioral;

- - - Updated - - -

Simulation result s.png

- - - Updated - - -

Simulation result s.png

- - - Updated - - -

out file content after simulation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
 

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Active high write1:
Code:
IF(CLK'EVENT AND CLK='1') THEN 
if(write1 = '1')then

in TB write is hard coded to never write:
Code:
   signal write1 : bit := '0';

Therefore you never write to the ROM (why the heck is this called a ROM, i.e. Read Only Memory?)

But the code in the testbench should still write whatever is on datao every 60 ns so the output file should have more than a single line of written data.

What does the contents of the output data file look like? You say it has only one line of data in it.
 

Tetik

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In your simulation results, the clk signal is not toggling. Make sure that the clk is toggling.
 

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Okay never mind you posted the file contents, which is exactly what I expected, the TB is writing multiple datao values to the file, the data is just always 0 (which you didn't make at all clear).


Code VHDL - [expand]
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write1 <= '1' after 200 ns; -- you should probably modify this line and do this when you have new input data.
 
process (clk)
begin
  if rising_edge(clk) then
    if (write1 = '1') then
      address <= address + 1; -- you figure out the bit_vector conversions to make this work
                              -- you need to be more careful what types you use.
    end if;
  end if;
end



add the above code, which might work to get the ROM :)roll:) writes to occur.

- - - Updated - - -

In your simulation results, the clk signal is not toggling. Make sure that the clk is toggling.

I suspect they did not zoom out the simulation, and this is the low cycle of the clock showing something like 8 ps of the waveform.

When I ran their testbench it generates a clock and writes to the file with the same multiple lines of 0 data.
 

MSAKARIM

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Rom " just a name " :smile:
Ok, i'll try it now
 

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Rom " just a name " :smile:
Ok, i'll try it now

No, in HDL names are not "just a name", they are really part of the documentation of a design. If the name does not represent the function then the name is meaningless and might as well be xy7wzqfeg1 through xatyfdn2000. This is where so many junior people make a huge mistake in their code using meaningless names. Names should be chosen so code can be read and understood by someone not familiar with the code. Same goes for the comments, which there should optimally more lines of comments than there is of actual HDL code. The only time this isn't mandatory is when the code is beyond simple (but if it is that simple it probably shouldn't be in it's own file).
 

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