[SOLVED] VHDL simulation: $display vs report

[LatticeSemiconductor]

Hello all,

i have a testbench written in verilog that does the following:

---

Code Verilog - [expand]
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initial
begin
 
    $display(" ") ;
    $display(" !!!!!!!!!!  Starting Tests  !!!!!!!!!!");
    $display(" ") ;
    $display(" ") ;
    $display(" ") ;
    $display(" ") ;
    $display("    operating @ 1MHz in Mode 1") ;
    $display(" ") ;
    $display("    Device Under Test operating in mode 1") ;
    $display(" ") ;
 
end

---

## Aldec Simulator View Output:

# KERNEL:
# KERNEL: !!!!!!!!!! Starting Tests !!!!!!!!!!
# KERNEL:
# KERNEL:
# KERNEL:
# KERNEL:
# KERNEL: operating @ 1MHz in Mode 1
# KERNEL:
# KERNEL: Device Under Test operating in mode 1
# KERNEL:

what i want is pretty much the same, for my VHDL testbench. I simply replaced $display with a report statement:

---

Code VHDL - [expand]
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init : process
  begin
    report " " ;
    report " !!!!!!!!!!  Starting Tests  !!!!!!!!!!" ;
    report " " ;
    report " " ;
    report " " ;
    report " " ;
    report "    operating @ 1MHz in Mode 1" ;
    report " " ;
    report "    Device Under Test operating in mode 1" ;
    report " " ;
    wait;
  end process ; -- init

---

## Aldec Simulator View Output:

# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE : !!!!!!!!!! Starting Tests !!!!!!!!!!
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE : operating @ 1MHz in Mode 1
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE : Device Under Test operating in mode 1
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# EXECUTION:: NOTE :
# EXECUTION:: Time: 0 ps, Iteration: 0, Instance: /core1GbE_tb, Process: init.
# KERNEL: stopped at time: 165 ns

I am using the Aldec Active HDL Simulator, and the output is not readable. I dont understand why it behaves different. How can i remove time and process indications?

thanks

 

[SynthWorks]

Unfortunately report does not work so well. You might create a package like following :

use std.textio.all ; 
package TextUtil is
  procedure Print(s : string) ;
end package TextUtil ; 
package body TextUtil is
  procedure Print(s : string) is 
    variable buf : line ; 
  begin
    write(buf, s) ; 
    WriteLine(OUTPUT, buf) ; 
  end procedure Print ; 
end package body TextUtil ;

Then your testbench can do:

    Print(" ") ;
    Print(" !!!!!!!!!!  Starting Tests  !!!!!!!!!!");
    Print(" ") ;

If you are doing much testbench coding in VHDL, you might check out the OSVVM libraries (https://www.osvvm.org).

The next revision of OSVVM (due early February) will have a Transcripting package (which will have the above and more) as well as an AlertLog package. Alerts and logs are similar to assert except they also give VHDL direct access to enabling and disabling of features, retrieving alert counts, and set stop counts (limits other than 1) - also the message prints in a single line.

 

[LatticeSemiconductor]

works like a charm.
many thanks for this, and your link :smile:

i am coding everything in VHDL, including the testbenches, but in times like this, i wish there would be something like "inline verilog" :-D