Question:
Why the "signal" prefix prior to the port name?
Because the Altera tools chose to have the IP output the optional keyword 'signal'. According to section 6.5.2 of the VHDL-2008 LRM....
6.5.2 Interface object declarations
An interface object declaration declares an interface object of a specified type. Interface objects include
interface constants that appear as generics of a
design entity, a component, a block, a package, or a
subprogram, or as constant parameters of subprograms;
interface signals that appear as ports of a design
entity, component, or block, or as signal parameters of subprograms; interface variables that appear as
variable parameters of subprograms; interface files that appear as file parameters of subprograms.
interface_object_declaration ::=
interface_constant_declaration
| interface_signal_declaration
| interface_variable_declaration
| interface_file_declaration
interface_constant_declaration ::=
[ constant ] identifier_list : [ in ] subtype_indication [ := static_expression ]
interface_signal_declaration ::=
[
signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ := static_expression ]
interface_variable_declaration ::=
[ variable ] identifier_list : [ mode ] subtype_indication [ := static_expression ]
The 2002 LRM isn't quite as succinct, but seems to be equivalent in this regard.
Kevin Jennings
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this is AMS VHDL module (it can have) you can treat ports as signals quantities or terminals
No, this is straight VHDL.
Kevin