VHDL signal port declaration

[shaiko]

Hello,

This code is generated via Altera's IP catalog:

entity knn_example_top is 
port (
-- inputs:
   [COLOR="#FF0000"]signal[/COLOR] clock_source : IN STD_LOGIC;
   signal global_reset_n : IN STD_LOGIC;

-- outputs:
   signal mem_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
   signal mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
   signal mem_cas_n : OUT STD_LOGIC;
   signal mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_dm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
   signal mem_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
   signal mem_dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
   signal mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_ras_n : OUT STD_LOGIC;
   signal mem_we_n : OUT STD_LOGIC;
   signal pnf : OUT STD_LOGIC;
   signal pnf_per_byte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
   signal test_complete : OUT STD_LOGIC;
   signal test_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end entity knn_example_top;

Question:
Why the "signal" prefix prior to the port name?

 

[aruipksni]

Hello,

This code is generated via Altera's IP catalog:

entity knn_example_top is 
port (
-- inputs:
   [COLOR="#FF0000"]signal[/COLOR] clock_source : IN STD_LOGIC;
   signal global_reset_n : IN STD_LOGIC;

-- outputs:
   signal mem_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
   signal mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
   signal mem_cas_n : OUT STD_LOGIC;
   signal mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_dm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
   signal mem_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
   signal mem_dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
   signal mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
   signal mem_ras_n : OUT STD_LOGIC;
   signal mem_we_n : OUT STD_LOGIC;
   signal pnf : OUT STD_LOGIC;
   signal pnf_per_byte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
   signal test_complete : OUT STD_LOGIC;
   signal test_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end entity knn_example_top;

Question:
Why the "signal" prefix prior to the port name?

this is AMS VHDL module (it can have) you can treat ports as signals quantities or terminals

 

[shaiko]

Quantities or Terminals ? What does that mean ?
Please elaborate

 

[FvM]

If you want to learn about VHDL-AMS (VHDL analog and mixed-signal extension), you can search the internet. https://en.wikipedia.org/wiki/VHDL-AMS

The shown port definition doesn't make sense however.
- Altera doesn't support AMS
- A circuit with only signal ports has no analog functions, it won't be modelled in VHDL AMS

How did you generate this VHDL text?

 

[shaiko]

How did you generate this VHDL text?

While playing with Altera's IP Catalog - Cyclone IV DDR Memory Controllers.

 

[K-J]

Question:
Why the "signal" prefix prior to the port name?

Because the Altera tools chose to have the IP output the optional keyword 'signal'. According to section 6.5.2 of the VHDL-2008 LRM....
6.5.2 Interface object declarations
An interface object declaration declares an interface object of a specified type. Interface objects include
interface constants that appear as generics of a design entity, a component, a block, a package, or a
subprogram, or as constant parameters of subprograms; interface signals that appear as ports of a design
entity, component, or block, or as signal parameters of subprograms; interface variables that appear as
variable parameters of subprograms; interface files that appear as file parameters of subprograms.
interface_object_declaration ::=
interface_constant_declaration
| interface_signal_declaration
| interface_variable_declaration
| interface_file_declaration
interface_constant_declaration ::=
[ constant ] identifier_list : [ in ] subtype_indication [ := static_expression ]
interface_signal_declaration ::=
[ signal ] identifier_list : [ mode ] subtype_indication [ bus ] [ := static_expression ]
interface_variable_declaration ::=
[ variable ] identifier_list : [ mode ] subtype_indication [ := static_expression ]

The 2002 LRM isn't quite as succinct, but seems to be equivalent in this regard.

Kevin Jennings

- - - Updated - - -

this is AMS VHDL module (it can have) you can treat ports as signals quantities or terminals

No, this is straight VHDL.

Kevin

 

[FvM]

Because the Altera tools chose to have the IP output the optional keyword 'signal'. According to section 6.5.2 of the LRM....

Yes, I see. But the purpose is still mysterious. As far as I'm aware of, the optional keyword doesn't appear in any IEEE 1076 example, only in the formal language definition part. I neither saw it in any Altera IP before.