shaiko
Advanced Member level 5

Hello,
This code is generated via Altera's IP catalog:
Question:
Why the "signal" prefix prior to the port name?
This code is generated via Altera's IP catalog:
Code:
entity knn_example_top is
port (
-- inputs:
[COLOR="#FF0000"]signal[/COLOR] clock_source : IN STD_LOGIC;
signal global_reset_n : IN STD_LOGIC;
-- outputs:
signal mem_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
signal mem_cas_n : OUT STD_LOGIC;
signal mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_dm : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal mem_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal mem_dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
signal mem_ras_n : OUT STD_LOGIC;
signal mem_we_n : OUT STD_LOGIC;
signal pnf : OUT STD_LOGIC;
signal pnf_per_byte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal test_complete : OUT STD_LOGIC;
signal test_status : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end entity knn_example_top;
Question:
Why the "signal" prefix prior to the port name?