VHDL Signal Aggregation and its opposite

[wtr]

Hello all,

I'm a bit of a purest & want symetry in my coding. Please tell me if there is a better way to do the decomposing of a signal

-- Recompose whole using parts
                
cid_reg <= (127 DOWNTO 120 => mid,        -- Manufacturers      
            119 DOWNTO 114 => cid_r1,     -- Reserved           
            113 DOWNTO 112 => cbx,        -- Device/BGA         
            111 DOWNTO 104 => oid,        -- OEM/Application ID 
            103 DOWNTO  56 => pnm,        -- Product Name       
             55 DOWNTO  48 => prv,        -- Product Revision   
             47 DOWNTO  16 => psn,        -- Product Serial     
             15 DOWNTO   8 => mdt,        -- Manufacturing date 
              7 DOWNTO   1 => crc,        -- CRC7 Checksum      
                         0 => cid_always  -- always 1           
            )
            
-- Decompose whole to create parts

mid    <= cid_reg(127 DOWNTO 120);
cid_r1 <= cid_reg(119 DOWNTO 114);
...
...
--There has got to be a better way
...

Regards,
Wes

 

[TrickyDicky]

what exactly do you mean by symmetry? from this code, you're likely to get multiple driver errors.

 

[ads-ee]

The OP is trying to bit slice and reassemble a large vector.

I suggest using a record then you don't have to deal with reassembling the large vector. The record itself would be the cid_reg.

 

[K-J]

Hello all,

I'm a bit of a purest & want symetry in my coding. Please tell me if there is a better way to do the decomposing of a signal

<snip>
...
...
--There has got to be a better way
...

Here is my way...

type t_CID_REG is record
    Manufacturers:      std_ulogic_vector(127 downto 20);
    Reserved:           std_ulogic_vector(119 downto 114);
    Device:             std_ulogic_vector(113 downto 112);
    Application:        std_ulogic_vector(111 downto 104);
    Product_Name:       std_ulogic_vector(103 downto 56);
    Product_Revision:   std_ulogic_vector(55 downto 48);
    Product_Serial:     std_ulogic_vector(47 downto 16);
    Mfg_Date:           std_ulogic_vector(15 downto 8);
    CRC7_Checksum:      std_ulogic_vector(7 downto 1);
    Always1:            std_ulogic_vector(0 downto 0);
end record t_CID_REG;

function To_Std_ULogic_Vector(L : t_CID_REG) return std_ulogic_vector is
    variable RetVal:    std_ulogic_vector(127 downto 0);
begin
    RetVal(L.Manufacturers'range)   := L.Manufacturers;
    RetVal(L.Reserved'range)        := L.Reserved;
    RetVal(L.Device'range)          := L.Device;
    RetVal(L.Application'range)     := L.Application;      
    RetVal(L.Product_Name'range)    := L.Product_Name;
    RetVal(L.Product_Revision'range):= L.Product_Revision;
    RetVal(L.Product_Serial'range)  := L.Product_Serial;
    RetVal(L.Mfg_Date'range)        := L.Mfg_Date;
    RetVal(L.CRC7_Checksum'range)   := L.CRC7_Checksum;
    RetVal(L.Always1'range)         := L.Always1;

    return(RetVal);
end function To_Std_ULogic_Vector;

function From_Std_ULogic_Vector(L : std_ulogic_vector) return t_CID_REG is
    variable RetVal:    t_CID_REG;
    constant Lx:        std_ulogic_vector(L'length - 1 downto 0) := L;
begin
    RetVal.Manufacturers    := Lx(RetVal.Manufacturers'range);
    RetVal.Reserved         := Lx(RetVal.Reserved'range);
    RetVal.Device           := Lx(RetVal.Device'range);
    RetVal.Application      := Lx(RetVal.Application'range);
    RetVal.Product_Name     := Lx(RetVal.Product_Name'range);
    RetVal.Product_Revision := Lx(RetVal.Product_Revision'range);
    RetVal.Product_Serial   := Lx(RetVal.Product_Serial'range);
    RetVal.Mfg_Date         := Lx(RetVal.Mfg_Date'range);
    RetVal.CRC7_Checksum    := Lx(RetVal.CRC7_Checksum'range);
    RetVal.Always1          := Lx(RetVal.Always1'range);

    return(RetVal);
end function From_Std_ULogic_Vector;

Kevin Jennings

 

[wtr]

You sir are my hero.
Thank you