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[SOLVED] VHDL - shifting std_logic_vector by 8 bits

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yttuncel

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Hello,

I've managed to solve the issues on my old topic, and here is a newer one. I want to scroll the text I've written on the seven segment display wrto clock, but system clock too fast. I tried to mux the clocks but I got multiple clocks error. Now I am trying to do it by counter. Here is the code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
 
entity my_shifter is
        port(clk      : in  std_logic;
                doShift : in std_logic;--input to determine shifting(0>shifts when a new char is available, 1>shifts 1 digit per second, no datains)
                Scan_Dav : in  std_logic;--from keyboard, data is ready
                Data_in  : in  std_logic_vector (7 downto 0);--scancode
                O1 : out std_logic_vector(7 downto 0);
                O2 : out std_logic_vector(7 downto 0);
                O3 : out std_logic_vector(7 downto 0);
                O4 : out std_logic_vector(7 downto 0)
                );
end my_shifter;
 
architecture bhv of my_shifter is
 
signal bytes : std_logic_vector(63 downto 0):=(others => '0');
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
signal shift : std_logic:='0';
signal flag : std_logic:='0';
signal first_letter: std_logic_vector(7 downto 0):="00000000";
begin
    process(clk)
        variable var:integer range 0 to 50000000 :=0;
        begin
            if rising_edge(clk) then
                if var = 50000000 then
                    var:=0;
                    flag<='0';
                    shift <= '1';
                else
                    flag <= '1';
                    var:=var+1;
                    shift <= '0';
                end if;
            end if;
    end process;
    
    process (clk, doShift, flag, shift) 
        begin
            case doShift is
            
                when '0' =>
                    if rising_edge(clk) then
                        Scan_Dav_Sync(0) <= Scan_Dav;
                        Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
                        Previous_Scan_Dav <= Scan_Dav_Sync(1);
                        if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
                            bytes <= bytes (bytes'high-8 downto 0) & Data_in;
                        end if;
                    end if;
                    -- works fine till here
                when '1' =>
                    if (shift = '1' and flag = '0' ) then
                        first_letter <= bytes(bytes'high downto bytes'high-7);
                        bytes <= bytes (bytes'high-8 downto 0) & first_letter;
                    end if; 
                    
                when others =>--just ignore here
                    bytes <= bytes (bytes'high-8 downto 0) & Data_in;
                    
            end case;
    end process;
    O1 <= bytes(31 downto 24);
    O2 <= bytes(23 downto 16);
    O3 <= bytes(15 downto 8);
    O4 <= bytes(7 downto 0);
end bhv;



The problem is when I toggle the pin of doShift, I get random characters on seven segment display. What is the error here?
 
Last edited:

when I toggle the pin of doShift, I get random characters on seven segment display
Most synthesis tools will generate warnings for the latches generated with bytes and first_letter and complain that the bytes value isn't kept between clock cycles.

To make the design work, you should change two things:
- enclose the whole case doShift construct by a clock edge sensitive condition, not only the when '0' code.
- synchronize doShift to the clock, similar to Scan_Dav.

The others case can be empty, because it's never true in synthesized logic (presuming it's required at all by your synthesis tool).
 

Thank you for your answer, I've completed my project, and it works flawlessly.
 

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