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[SOLVED] VHDL Shift Register with enable problem

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indu15

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I am implementing serial in serial out 72 bit shift register using VHDL. When the enable signal is high, I want the shift register to shift 72 times, irrespective of whether enable continues to be high or low. I have written the following code which is working only when the enable is high. Can anyone please let me know how to shift data once enable is high and then does not depend on enable to shift the data?

-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SR is
port(clk, din, rst, enable : in std_logic;
sr_out : inout std_logic_vector(71 downto 0));

end SR;

architecture behavioral of SR is

signal shift_reg: std_logic_vector(71 downto 0);
begin
process (clk, rst)
begin
if (rst = '0') then
shift_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if enable= '1' then
shift_reg(70 downto 0) <= shift_reg(71 downto 1);
shift_reg(71) <= din;
end if;
end if;

end process;

sr_out <= shift_reg;

end behavioral;


Thanks a lot!
 

u can make a simple register that holds the previous and current signal enable data and generates impulse in '0'&'1' condition that will starts the counter to 72 ( that counter process will generate 'true_enable' signal to your shift_register block for 72 cycles)
 

Thanks for the reply axcdd. I am newbie to VHDL. what do you mean by "generates impulse in '0'&'1' condition that will starts the counter to 72"?
 

HI,

I agree to "axcdd". You need to create another signal aka 'true_enable' that will register the change of the 'enable' signal.
(what I guess from ur post is that 'enable' signal will be togelling and once it is high shifting should take place).

In ur code, u r shifting only when enable is HIGH and clk is HIGH.
First write the logic that 'true_enable' will be high when 'enable' is high. Make sure to also define the logic that 'true_enable' will not be LOW when 'enable'
goes LOW. After this use ur shifting logic by checking the HIGH condition of the 'true_enable' signal.
*** Make sure that you change back 'true_enable' to LOW after your shifting operation is over (this will help you if this logic is a part of a bigger design block).

Hope I have answered this correctly & helps you.
I would appreciate if some senior member approves what I have written & point out if there are potential mistakes.

cheers,
DP
 

what you're trying to build is an edge detector - you're trying to detect the rising edge of the "en" signal, and then waiting 72 clock cycle. To do this, you just need to register enable, compare the registered version to the input and then set a counter off that will "disable" the new enable signal.

SOmething liuke:

Code:
process(clk)
begin
if rising_edge(clk) then
  en_r <= en;
  if en = '1' and en_r = '0' then -- check for rising_edge
    trig_shift = '1';
  elsif cnt = 72 then
    trig_shift <= '0';
  end if;

  if trig_shift = '0' then
    cnt <= 0;
  elsif trig_shift = '1' then
    --do a shift
    cnt <= cnt + 1;
  end if;
end if;
end process;
 
Other way is to use FSM...in which in 1st state you check for valid enable.... If enable is there move to next state and start serial shifting...continue shifting for 72 bits....once completed come back to 1st state or to load new data to 72 bit register.....FSM ensures your synchronouse operation...
 

Other way is to use FSM...in which in 1st state you check for valid enable.... If enable is there move to next state and start serial shifting...continue shifting for 72 bits....once completed come back to 1st state or to load new data to 72 bit register.....FSM ensures your synchronouse operation...

Seems a little overcomplicated - you still need a counter to count to 72.
 

Thank you all for the help. Trickydicky your code is very helpful.
 

In Both the cases you have to count 72 bits that is obvious....FSM will ensure that control will not go to first enable state every time...as in other case..
 

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