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Code VHDL - [expand] 1 reg2 <= reg1;
Code VHDL - [expand] 1 reg2(0) <= reg1(0); -- assuming reg1/2 are arrays where 0th element is first bit
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 library ieee; use ieee.std_logic_1164.all; entity test3 is port(clk: in std_logic; ifc_a: out std_logic_vector(1 downto 0)); end test3; architecture modu of test3 is signal ifc_dout: std_logic_vector(1 downto 0); begin process(clk) then begin if(rising_edge(clk)) then ifc_a(0)<=ifc_dout(0); ifc_a(1)<=ifc_dout(1); end if; end process; end modu;
how to transfer the bits of one register to another register in vhdl?
You should figure out the question before you ask.but i want to transfer the first bit of reg1 to first bit of reg2..
ifc_a(0)<=ifc_dout(0);
ifc_a(1)<=ifc_dout(1);
ifc_a<=ifc_dout;
reg1(2:3) <= reg2(3:4);
is this valid in vhdl?
then how can i transfer the 2nd and 3rd bits of reg1 to 3rd and 4th bits of reg2?No, it is not.
thanks for your reply, but when i simulate the code it is showing an errorby writing valid VHDL:
reg1(2 to 3) <= reg2(3 to 4);
then how can i transfer the 2nd and 3rd bits of reg1 to 3rd and 4th bits of reg2?
you keep asking variants of the same question that is utterly basic. please read a book or a tutorial on vhdl.
Besides that, switching constantly between Verilog and VHDL isn't going to help you learn either language. Pick one and learn just that one language. Once you are familiar (I don't mean you can recognize the language) with designing in that language and are comfortable with using it, then and only then, should you start studying the other language.
signal a : std_logic_vector(0 to 3);
signal b : std_logic_vector(1 to 4);
signal c : std_logic_vector(3 downto 0);
signal d : std_logic_vector(7 downto 4);
a <= "X10Z"; -- a(0) = 'X', a(1) = '1'; a(2) = '0', a(3) = 'Z'; -- a(3) is the leftmost bit
b <= a; -- b(0) is an error. b(1) = 'X', b(2) = '1', b(3) = '0', b(4) = 'Z';
c <= a; -- c(0) = 'Z', c(1) = '0', c(2) = '1', c(3) = 'X'; -- c(0) is the leftmost bit
d <= a; -- d(0), d(1), d(2), d(3) are not valid. d(4) = 'Z', d(5) = '0', d(6) = '1', d(7) = 'X'