Re: VHDL "register" reseved word
In VHDL, what is the reseved word "register" used for ?
Per the LRM...
B.209 register: A kind of guarded signal that retains its last driven value when all of its drivers are turned off. (§4.3.1.2)
This is different than 'bus' which the LRM defines as...
B.38 bus: One kind of guarded signal. A bus floats to a user-specified value when all of its drivers are turned off. (§4.3.1.2, §4.3.2)
These seem to be the only types of guarded signals since the LRM defines...
B.117 guarded signal: A signal declared as a register or a bus. Such signals have special semantics when their drivers are updated from within guarded signal assignment statements. (§4.3.1.2)
Which brings us to what is a 'guarded signal assignment statements' which the LRM defines as...
B.116 guarded assignment: A concurrent signal assignment statement that includes the option guarded, which specifies that the signal assignment statement is executed when a signal GUARD changes from FALSE to TRUE, or when that signal has been TRUE and an event occurs on one of the signals referenced in the corresponding GUARD expression. The signal GUARD must be one of the implicitly declared GUARD
signals associated with block statements that have guard expressions, or it must be an explicitly declared signal of type Boolean that is visible at the point of the concurrent signal assignment statement. (§9.5)
At this point, I give up since I've never found the need to use a guarded signal assignment in synthesizable or testbench code. Maybe I could find it useful, but to this point I haven't. Run of the mill signal assignments retain their last value until they hit a new assignment...so what exactly a 'guarded register signal' or a 'guarded bus signal' brings to the table as far as being a better way to write code isn't very obvious...if it's not better, don't bother with it.
Kevin Jennings
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IIRC, it was meant to allow you to implement a register without a process.
For the cases where I just want to register some signal, I like this method...simple and concise.
Q <= D when rising_edge(Clock);
Kevin Jennings