VHDL "register" reseved word

[shaiko]

In VHDL, what is the reseved word "register" used for ?

 

[TrickyDicky]

IIRC, it was meant to allow you to implement a register without a process. Its so unused I cannot even find an example of how to use it.
Probably a good idea back in the early 80s, but it never caught on..

 

[shaiko]

BTW,

Is there ever going to be any support for VHDL 2008 by synthesis tools ?

 

[std_match]

"register" can be used to declare a "guarded signal".
I don't see any use for it in FPGA design.
"register" can be used to simulate "dynamic logic", where all drivers can be disconnected, and the previous value will be kept by the capacitance: https://en.wikipedia.org/wiki/Dynamic_logic_(digital_electronics)

Here is some information about guarded signals: https://books.google.se/books?id=Xb...733#v=onepage&q=vhdl "guarded signal"&f=false

 

[K-J]

Re: VHDL "register" reseved word

In VHDL, what is the reseved word "register" used for ?

Per the LRM...
B.209 register: A kind of guarded signal that retains its last driven value when all of its drivers are turned off. (§4.3.1.2)

This is different than 'bus' which the LRM defines as...
B.38 bus: One kind of guarded signal. A bus floats to a user-specified value when all of its drivers are turned off. (§4.3.1.2, §4.3.2)

These seem to be the only types of guarded signals since the LRM defines...
B.117 guarded signal: A signal declared as a register or a bus. Such signals have special semantics when their drivers are updated from within guarded signal assignment statements. (§4.3.1.2)

Which brings us to what is a 'guarded signal assignment statements' which the LRM defines as...
B.116 guarded assignment: A concurrent signal assignment statement that includes the option guarded, which specifies that the signal assignment statement is executed when a signal GUARD changes from FALSE to TRUE, or when that signal has been TRUE and an event occurs on one of the signals referenced in the corresponding GUARD expression. The signal GUARD must be one of the implicitly declared GUARD
signals associated with block statements that have guard expressions, or it must be an explicitly declared signal of type Boolean that is visible at the point of the concurrent signal assignment statement. (§9.5)

At this point, I give up since I've never found the need to use a guarded signal assignment in synthesizable or testbench code. Maybe I could find it useful, but to this point I haven't. Run of the mill signal assignments retain their last value until they hit a new assignment...so what exactly a 'guarded register signal' or a 'guarded bus signal' brings to the table as far as being a better way to write code isn't very obvious...if it's not better, don't bother with it.

Kevin Jennings

- - - Updated - - -

IIRC, it was meant to allow you to implement a register without a process.

For the cases where I just want to register some signal, I like this method...simple and concise.
Q <= D when rising_edge(Clock);

Kevin Jennings

 

[TrickyDicky]

BTW,

Is there ever going to be any support for VHDL 2008 by synthesis tools ?

Probably. But only if enough people ask for it. (so get asking for it...)
Quartus supports some parts of 2008.

http://quartushelp.altera.com/current/mergedProjects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

And I thought Synplify had decent 2008 support?

 

[std_match]

Re: VHDL &quot;register&quot; reseved word

Run of the mill signal assignments retain their last value until they hit a new assignment...so what exactly a 'guarded register signal' or a 'guarded bus signal' brings to the table as far as being a better way to write code isn't very obvious...if it's not better, don't bother with it.

There is a difference when you have multiple processes driving the same signal.
When all processes drives a normal std_logic signal with 'Z', the result is 'Z'.
When all drivers disconnect from a "register" signal, the previous resolved value is kept.
This kept value can be '0', '1', 'Z' or whatever.
It is also not like a latch, since there is no active driver. As soon as any driver is connected again it will have full control over the signal.
This means that the guarded signal can be '1' (all drivers disconnected), and any driver can connect and drive it to '0' without a conflict.

Again, I don't see any use for it in FPGA design, because modern FPGA's don't have any internal hardware that function like guarded signals.

The guarded signal of type "bus" is similar, bit instead of keeping the previous value when all drivers disconnect, the signal is "pulled" to a predefined value.
Maybe it could be useful to simulate the bidirectional data line of an I2C bus, which have a pull-up resistor.

Disclaimer:
I have not used guarded signals, so what I have written can be wrong.

 

[K-J]

Re: VHDL &quot;register&quot; reseved word

There is a difference when you have multiple processes driving the same signal.
When all processes drives a normal std_logic signal with 'Z', the result is 'Z'.
When all drivers disconnect from a "register" signal, the previous resolved value is kept.
This kept value can be '0', '1', 'Z' or whatever.

This is exactly the same behaviour as your 'normal' signal assignment. The value that is 'kept' for the signal is simply the last value driven, whether that assignment comes from a 'guarded' signal assignment or a 'non-guarded' assignment. If that last assignment is '0', the signal will be '0', if it's 'Z' it will be 'Z'.

From the LRM's perspective, I don't think the phrase "all of its drivers are turned off" has the same meaning as it would be from an electrical perspective where it would typically mean that all drivers are tri-stated. Just using normal signal assignments, every process that connects to a signal is always driving that signal with something. The resolution function is what takes all of those driving values and determines the final driven value for the signal.

Besides, driving a signal to a value of 'Z' can't mean the same thing as 'all of its drivers are turned off' because the phrase 'all of its drivers are turned off' is part of the language definition itself where as type std_logic/std_ulogic which defines 'Z' with the meaning used for a tri-state is defined in the std_logic_1164 package. That package depends on the LRM, the LRM does not depend on that package.

Kevin Jennings

 

[std_match]

Re: VHDL &quot;register&quot; reseved word

This is exactly the same behaviour as your 'normal' signal assignment. The value that is 'kept' for the signal is simply the last value driven, whether that assignment comes from a 'guarded' signal assignment or a 'non-guarded' assignment. If that last assignment is '0', the signal will be '0', if it's 'Z' it will be 'Z'.

It is not the same. For a normal signal each driver keeps it's own value. A "register" signal keeps a value by itself when all drivers are disconnected.

From the LRM's perspective, I don't think the phrase "all of its drivers are turned off" has the same meaning as it would be from an electrical perspective where it would typically mean that all drivers are tri-stated. Just using normal signal assignments, every process that connects to a signal is always driving that signal with something. The resolution function is what takes all of those driving values and determines the final driven value for the signal.

A guarded std_logic is similar to a normal std_logic with an extra "weak" driver, which only has effect when all other drivers are driving 'Z'.
For "register" the weak driver is trying to keep the current value, and for "bus" it is trying to pull-up, pull-down or pull to some other constant value.

Besides, driving a signal to a value of 'Z' can't mean the same thing as 'all of its drivers are turned off' because the phrase 'all of its drivers are turned off' is part of the language definition itself where as type std_logic/std_ulogic which defines 'Z' with the meaning used for a tri-state is defined in the std_logic_1164 package. That package depends on the LRM, the LRM does not depend on that package.

I agree, it is not the same thing. If all drivers drive a normal signal to 'Z', the result will be 'Z'.
If all drivers are disconnected from a guarded signal, it can still have a valid value like '0' or '1'.

Here is an example with 2 processes controlling the same signals.
One process only assigns '1', and the other process only assigns '0', in 1 us long pulses:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity test_guarded_signals is
end test_guarded_signals;
 
architecture sim of test_guarded_signals is
  signal test_guarded_register : std_logic register;
  signal test_guarded_bus : std_logic bus;
  signal driving_0 : std_logic := '0';
  signal driving_1 : std_logic := '0';
begin
  
  -- process for setting bits
  process
  begin
    wait for 5 us;
    test_guarded_register <= '1';
    test_guarded_bus <= '1';
    driving_1 <= '1';
    wait for 1 us;
    test_guarded_register <= null; -- A null assignment disconnects the driver
    test_guarded_bus <= null;
    driving_1 <= '0';
    wait for 10 us;
    test_guarded_register <= '1';
    test_guarded_bus <= '1';
    driving_1 <= '1';
    wait for 1 us;
    test_guarded_register <= null;
    test_guarded_bus <= null;
    driving_1 <= '0';
    wait for 1 us;
    wait;
  end process;
  
  -- process for clearing bits
  process
  begin
    test_guarded_register <= null;
    test_guarded_bus <= null;
    wait for 10 us;
    test_guarded_register <= '0';
    test_guarded_bus <= '0';
    driving_0 <= '1';
    wait for 1 us;
    test_guarded_register <= null;
    test_guarded_bus <= null;
    driving_0 <= '0';
    wait;
  end process;
end sim;

---

I have attached a picture with the simulation result. The "register" signal keeps it's value between the "set" and "clear" pulses.
The "bus" signal goes to 'Z' when both drivers are disconnected, but there is no 'Z' assignment in the code.