VHDL Records equivalent in Verilog

[imbichie]

Hi All,

In VHDL Record is there for combining two or more signals/ports and we can call the records in a single name of representation.

So in Verilog is there any equivalent keyword for the same.

Thanks in Advance

 

[ads_ee]

The closest approximation is an interface, but I haven't run across any vendor tools that support it for synthesis. For simulation purposes it seems to be supported by the big vendors.

 

[dave_59]

SystemVerilog has structures, which are synthesizable by most tools that claim support for SystemVerilog. Interfaces are also part of SystemVerilog, and are synthesizable as well, but they are not data types like a structure is.