VHDL readwritememory-student

[draaknar]

19 Hours Ago

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Code VHDL - [expand]
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library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.assembler_code.all;
use work.cpu_package.all;
 
 
 
ENTITY RW_MEMORY IS
PORT( adr : IN adress_bus;
data : INOUT data_bus;
clk : IN std_logic;
ce : IN std_logic; -- active low
rw : IN std_logic); -- read on high
END ENTITY RW_MEMORY;
ARCHITECTURE Behaviour OF RW_MEMORY IS
 
type rwm_type is array(0 to 2**(adress_bus'length)-1) of std_logic_vector(3 downto 0);
 
signal regs: rwm_type:=(others=>(others=> '0'));
signal test: std_logic_vector(1 downto 0);
signal data_temp: std_logic_vector(3 downto 0);
begin
 
test <= ce&rw; --This is my signal which i use for ce and rw together.
 
process(test,data_temp)
 
begin
 
if test ="00" then
data_temp <= data;
elsif test= "01" then
data    <=  regs(to_integer(unsigned(adr)));
else
data <= (others => 'Z');
data_temp <= (others    => '0');
end if;
 
end process;
 
 
 
 
 
test1: process(clk)
begin
if rising_edge(clk) then
if test = "00" then
regs(to_integer(unsigned(adr))) <= data_temp;
end if;
end if;
end process;
 
 
end Behaviour;

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Hello, i got alot of latches wich i dont know how to remove, ive tried all kind of methods to remove the latches, but i cant get anywhere. The big problem here is that i get inferring latches for data and data temp.


Note that when test is "00" (write-mode ) it will just write when we clock and the value it writes is the data_temp which is equal to data. I would be very grateful if u gave me some hints or feedback to solve this problem and make the code Synthesizable.

regards

John Schaizar

 

[barry]

Every time you have an incomplete IF statement, you are going to generate a latch.
For starters, in this block:

if test ="00" then
         data_temp <= data;
elsif test= "01" then
         data	<=	regs(to_integer(unsigned(adr)));
else
         data <= (others	=> 'Z');
         data_temp <= (others	=> '0');
end if;

1) What's the value of data when test="00"?
2) What's the value of data_temp when test="01"?

 

[aruipksni]

Every time you have an incomplete IF statement, you are going to generate a latch.
For starters, in this block:

if test ="00" then
         data_temp <= data;
elsif test= "01" then
         data	<=	regs(to_integer(unsigned(adr)));
else
         data <= (others	=> 'Z');
         data_temp <= (others	=> '0');
end if;

1) What's the value of data when test="00"?
2) What's the value of data_temp when test="01"?

ofcourse your sensitivity list should be corrected -
it should include all inputs, output are not necessary.
also puting data in 'Z' is something i wouldn't write -
i would generate an output enable signal and connect to output buffer

 

[imbichie]

You will get latches, because you are not using the clk at all, if you are not including the clk in the sensitivity list, it will become combinational logic.
You can include the clk in the sensitivity list ans use the if (rising_edge(clk)).

Otherwise you should use else for all the if statement

 

[draaknar]

Yes I know, but im only supposed to use the clock when i write , and not when i read. Thats why i have two different process for read and write. We shouldnt be able to read and write simultaneously.

 

[barry]

We shouldn't be able to read and write simultaneously.

Why not? It's done all the time with dual-port memory. Further, why wouldn't you use the clock for reading? That, too, is done all the time.

Are these constraints that are imposed on you by someone else, or your own perceptions? Regardless, your initial question was about why you are getting latches and I think we've answered that.

And to clarify a few points:

1) You are not getting latches because you aren't using a clock, you are getting latches because you have an incomplete if statement.
2) Sensitivity lists only affect simulation.

 

[draaknar]

Yes it is constraints which are imposed by my professor, thats why the code structure is a little bit odd .I personally, would use the read and write mode in a process with a sync-clock. Anyway i think i have the answers for my problems. Thanks for the help.

 

[ads-ee]

Yes it is constraints which are imposed by my professor, thats why the code structure is a little bit odd .I personally, would use the read and write mode in a process with a sync-clock. Anyway i think i have the answers for my problems. Thanks for the help.

Sometimes I wonder if there are too may professors in universities that have never worked in industry and dealt with designs that look like something a college student produced for a digital design class. The professors seem to push non-standard (and poor) design practices by creating assignments that have ridiculous requirements. Like this asynchronous read with synchronous write.

Using code like this is practically guaranteed to reduce the maximum clock frequency of a design, especially if you read everything you wrote and you're writing nearly 100% of the time.

Regards

 

[barry]

Sometimes I wonder if there are too may professors in universities that have never worked in industry and dealt with designs that look like something a college student produced for a digital design class. The professors seem to push non-standard (and poor) design practices by creating assignments that have ridiculous requirements. Like this asynchronous read with synchronous write.

Using code like this is practically guaranteed to reduce the maximum clock frequency of a design, especially if you read everything you wrote and you're writing nearly 100% of the time.

Regards

I couldn't agree more. There seems to be so much emphasis in colleges on things like differentiating between 'structural' design or 'RTL' design, or "top down" versus "bottom up" design which, IMO, do nothing to help you do a create a good design. I'm not even sure WHAT form I use, and I've been creating successful designs for years.