VHDL question , How to make 2 architectures for 1 entity ?

[drdigital]

Hi All,

I want to make 2 architecture for 1 entity , selecting one of them by type of signal. when 1 activate first arch.when 2 activate the second

how can I do this ??

Thanks in advance

 

[omara007]

You can select the between 2 architectures using (configuration) statement.
In general, when you do synthesis you only implement one architecture. What you want to achieve shouldn't be implemented using 2 different architectures .. it's only one architecture and you can switch between your 2 circuits using a simple MUX. If the selector signal is '0' map the input/output ports to circuit-0 .. and when the selector signal is '1', map input/output ports to circuit-1. Still, both circuits are in one architecture. And you can change the MUX selector during the operation of the block/entity.

 

[drdigital]

OK, Thanks for your replay