VHDL question about using the internal if

[cippalippa]

Hello,

I have a question about vhdl, I have the following process:


signal contarow,minline,maxline: integer range 0 to 289;
signal vwina, vwin,rdenable,rd_rst2: std_logic;

v_VINDOW: process(contarow,minline,maxline,rdenable,rd_rst2)
begin
if ((rdenable and (not rd_rst2)) = '0') then
if ((contarow < minline) or (contarow > maxline)) then
vwin <= '1'; else vwin <= '0';
end if;
if ((contarow < minline+3) or (contarow > maxline-1)) then
vwina <= '1'; else vwina <= '0';
end if;
end if;
end process;

I would like to know if is possible to write the internal 'if' like verilog:

...
vwin <= ((contarow < minline) || (contarow > maxline));
...

so operation without the 'if' operator.
Thanks

D

 

[vlsi_whiz]

Re: VHDL question

You cant write it like in Verilog, but you can use the WHEN..ELSE statements in VHDL to write that since it is not a sequential clocked process.

 

[avimit]

Re: VHDL question

Yes, you can write in verilog style, but then you will have to use, the variable/signal which is being assigned as a 'boolean' type.
Say for example

signal myboolean : boolean;

myboolean <= (value1 > value2)

you can do you won expression in the above style.
Hope it helps,
kr,
Avi
http://www.vlsiip.com