Vhdl question: about the difference of variable and signal.

[ambar686]

I want to know when i have to use variable in a VHDL program and when i have to use signal in a program. Please help me.

 

[TrickyDicky]

Dont call VHDL a program. It is a description of hardware (VHSIC Hardware description language).

Variables can always be avoided. Always use signals until you are confident you know what you are doing.

Signals are assigned when a process suspends, variables are assigned immediatly. Signals in a clocked process will always map to a register, and outside a process map to a wire. Variables can map to different things depending on where they are assigned (hence why you need to be careful).

So there is no rule when to use a variable over a signal. It depends what logic you want and what you want the code to look like. Too many software programmers use variables because it makes their VHDL simulation behave like software. But they end up with terrible hardware.