[SOLVED] VHDL Proof of concept

[wtr]

Currently in the process of writing psuedo code

Would the following work?

TYPE nibble IS ARRAY(3 DOWNTO 0) OF STD_LOGIC;
TYPE byte   IS ARRAY(7 DOWNTO 0) OF STD_LOGIC;
TYPE byte_size IS RANGE (1 TO 1E15) OF byte
  UNITS
    B;
    KB = 1024 B;
    MB = 1024 KB;
    GB = 1024 MB;
    TB = 1024 GB;
  END UNITS;

Would byte_size give me a multi - array or would it generate lots of bytes concatenated together? or would it just not work?

Regards,
Wes

P.S where is the tag option to help people get hits of this question?

 

[FvM]

No idea what you want to achieve, but you can't relate physical types to bytes respectively bit vectors.

The third line is just illegal VHDL syntax.

 

[wtr]

I want to be able to write KB instead of std_logic_vector(1023 downto 0)

Or

Use in other words use blocks of data.

Therefore if I had 5 KB;s it would be 5 1024 byte blocks concatenated...or in an multidiminsional array.

 

[TrickyDicky]

Physical types are based on integer, not user defined types. So you'd be stuck from the start as FvM points out your physical type definition is illegal syntax.
Even if you did manage for force it, you'd probably struggle with support from synthesis tools.
You will also make your life really complicated defining your own array of std_logic, as type conversions would be needed for any interfacing to any other "normal" code, and you would have none of the standard functions you get with std_logic_vector (any boolean operation, to_X01 conversions etc).

Whats wrong with multi-dimensional arrays?

 

[wtr]

Thank you TrickyDicky. I will use a different approach