VHDL Problem Reply ASAP!

[surbhisuri]

Write VHDL description of the following combinational network as shown in Fig.1 using concurrent statements. Each gate has a 5 ns delay, excluding the inverter which has a 2-ns delay.
For fig, see attached doc file..

 

[barry]

Do your own damn homework. We're not here to do your work simply because you're too lazy to. Why did you even bother going to college? If you ever graduate, are you going to ask somebody to do your job for you, assuming you manage to convince someone to hire you?

Was that ASAP for you?

 

[mrflibble]

https://en.wikipedia.org/wiki/Work_ethic
https://en.wikipedia.org/wiki/Time_management

There we go, perfectly tailored to your VHDL problem. Apologies if this was not ASAP enough for you.

 

[barry]

https://en.wikipedia.org/wiki/Work_ethic
https://en.wikipedia.org/wiki/Time_management

There we go, perfectly tailored to your VHDL problem. Apologies if this was not ASAP enough for you.

Well, said, sir.