VHDL Problem in reading file HELP please

[MOOMOO_KAMP81]

in the below i have this runtime error :

no digits found in abstract literal
textio procedure READ(INTEGER): can not get value from "?" (? shows some unkhon character)


and then equal to the 16*16 times generate this error:
textio procedure READ(INTEGER) arameter L designate an empty string

what does it mean?



for i in 0 to 15 loop
for i in 0 to 15 loop
readline(my_input,my_inline);
read(my_inline,read_n);
int_vec(i)<=conv_std_vector(read_n,16);

end loop;
end loop;

 

[TrickyDicky]

It sounds like there is not enough data in the file, or there are characters that are not digits.

 

[MOOMOO_KAMP81]

i checked the data in file but it seems to be ok!

i dont know what should i do!!!!

 

[TrickyDicky]

are you sure you meant to have i in both loops? not i and j?

with what you have, you're only writing to 16 elements in an array, and you're overwriting the contents 16 times.

Are you sure there are 256 numbers in the file?

 

[MOOMOO_KAMP81]

in original code it is i,j i wrote it i in message for both its ok!

yes i wrote 256 data and each of them in one line and my rest of data from line 257 to ...

Added after 11 minutes:

here it is!




component Conv2 is
GENERIC (nxr, nxc: INTEGER :=16; n:INTEGER := 16; nmr: integer :=1; nmc: integer :=12);
port
(
clk :in std_logic;
x :in matrix(nxr-1 downto 0,nxc-1 downto 0);
y ut out_matrix( nxr - nmr downto 0,nxc-nmc downto 0);
filt: int_vector(nmc-1 downto 0)
);


end component Conv2;


signal clk : std_logic := '0';
signal ma : matrix (15 downto 0, 15 downto 0);
signal out_ma : out_matrix (15 downto 0, 4 downto 0);
signal int_vec : int_vector (11 downto 0);

begin
clk <= NOT clk after 10 ns;
-- _ma
--_int_vec

comp : Conv2 port map (
clk => clk,
x => ma,
filt => int_vec,
y => out_ma
);

process(clk)
variable temp : std_logic_vector(23 downto 0);
file my_input : text open READ_MODE is "SampleData.txt";
file my_output : text open WRITE_MODE is "ResultData.txt";

variable my_inline : line;
variable my_outline : line;
variable read_n : integer;
begin
if (rising_edge(clk)) then
if not (endfile(my_input)) then

--Readding Image
for i in 0 to 15 loop
for j in 0 to 15 loop

readline(my_input,my_inline);
read(my_inline,read_n);

ma(i,j)<= CONV_STD_LOGIC_VECTOR(read_n, 8);


end loop;
end loop;

--Reading Filter Kernel
for i in 0 to 15 loop
readline(my_input,my_inline);
read(my_inline,read_n);

int_vec(i) <= CONV_STD_LOGIC_VECTOR(read_n,16);

end loop;
end if;
end if;


if (falling_edge(clk)) then


for i in 0 to 14 loop
for j in 0 to 3 loop
temp := out_ma(i,j);
read_n := conv_integer(signed(temp));

write(my_outline,read_n);
writeline(my_output,my_outline);

end loop;
end loop;
end if;
end process;
end architecture;

 

[TrickyDicky]

Are you sure you have enough data in the file to cover ALL clock cycles in the simulation? you are reading 256 values EVERY clock cycle.

If you want to re-read the file:

The problem is that you are reading the entire file on every clock edge, without closing and restarting the file. You dont want to open the file when you declare it, you want to use the FILE_OPEN and FILE_CLOSE procedures:

file my_input : text;

--just before the loop:
FILE_OPEN(my_input, "SampleData.txt", read_mode);

--then after the loop:

FILE_CLOSE(my_input);

You dont need to do this with the output.

 

[rca]

dos or unix file input file ?

 

[MOOMOO_KAMP81]

hi ricky dick

i have 268 data or line,256 line for first double loop and 12 line for second single loop.


after closing the file, it will restart frombegining wont it?
and the next time start from the begining of file but after the the first double loop i need to read from line 256 to 268.

in the way that you said i think it will restart if i put file open before first and second loop!!!!

am i right?

Added after 56 seconds:

hi rca

my file is a simple txt file .

Added after 5 minutes:

hi ricky dicky i did your proposed way but i still have the same running error as i said in first message.

i dont know what should i do!!!

 

[TrickyDicky]

Without seeing more code, there isnt a lot we could do. It looks to me like your data file is too short, or it has illegal characters in it, or it is not a text file.

 

[falloutmx]

plz minimize your design and check.
if it works well, you should check your code.
if not,that is the file's problem

 

[MOOMOO_KAMP81]

hi fellas

my previous problems were solved by your helps. thanks



can you help me in finding synthesizable codes for fast adders or fast multiplier ,i need them for using in a convolution function.

 

[TrickyDicky]

can you help me in finding synthesizable codes for fast adders or fast multiplier ,i need them for using in a convolution function.

Fast is a relative term.

For me, A <= B*C; can work pretty fast.

 

[MOOMOO_KAMP81]

i mean for adder and multiplier for std_logic_vector . is the * operation do the multiply for signed ?

my numbers are eg: -472 which i convert them to 2'complement for doing arithmetic operation on them.

 

[TrickyDicky]

a std_logic_vector is not a number.

use the ieee.numeric_std library. It contains signed and unsigned data types. In that you'll find all the arithmatic functions for signed or unsigned.

You can just use integer if you want. If it really is an integer, just use an integer:

signal a, b, c : integer range -512 to 511;


c <= a*b;

 

[MOOMOO_KAMP81]

Re: VHDL Problem in multiply by * HELP please

now i want to use * for multiplying a matrix type and a std vector and the output that i need is std vector .


type matrix is array (nxr-1 downto 0,nxc-1 downto 0) of std_logic_vector(15 downnto 0)
type int_vector is array (integer range<> ) of std_logic_vector(7 downnto 0)


now i should multiply these types by * for using in convolution function.



plz help

 

[TrickyDicky]

please use unsigned type instead of std_logic_vector. you can convert it to std_logic_vector for the output.

 

[MOOMOO_KAMP81]

but my filter have some negative number?

 

[TrickyDicky]

then use signed.