in original code it is i,j i wrote it i in message for both its ok!
yes i wrote 256 data and each of them in one line and my rest of data from line 257 to ...
Added after 11 minutes:
here it is!
component Conv2 is
GENERIC (nxr, nxc: INTEGER :=16; n:INTEGER := 16; nmr: integer :=1; nmc: integer :=12);
port
(
clk :in std_logic;
x :in matrix(nxr-1 downto 0,nxc-1 downto 0);
y
ut out_matrix( nxr - nmr downto 0,nxc-nmc downto 0);
filt: int_vector(nmc-1 downto 0)
);
end component Conv2;
signal clk : std_logic := '0';
signal ma : matrix (15 downto 0, 15 downto 0);
signal out_ma : out_matrix (15 downto 0, 4 downto 0);
signal int_vec : int_vector (11 downto 0);
begin
clk <= NOT clk after 10 ns;
-- _ma
--_int_vec
comp : Conv2 port map (
clk => clk,
x => ma,
filt => int_vec,
y => out_ma
);
process(clk)
variable temp : std_logic_vector(23 downto 0);
file my_input : text open READ_MODE is "SampleData.txt";
file my_output : text open WRITE_MODE is "ResultData.txt";
variable my_inline : line;
variable my_outline : line;
variable read_n : integer;
begin
if (rising_edge(clk)) then
if not (endfile(my_input)) then
--Readding Image
for i in 0 to 15 loop
for j in 0 to 15 loop
readline(my_input,my_inline);
read(my_inline,read_n);
ma(i,j)<= CONV_STD_LOGIC_VECTOR(read_n, 8);
end loop;
end loop;
--Reading Filter Kernel
for i in 0 to 15 loop
readline(my_input,my_inline);
read(my_inline,read_n);
int_vec(i) <= CONV_STD_LOGIC_VECTOR(read_n,16);
end loop;
end if;
end if;
if (falling_edge(clk)) then
for i in 0 to 14 loop
for j in 0 to 3 loop
temp := out_ma(i,j);
read_n := conv_integer(signed(temp));
write(my_outline,read_n);
writeline(my_output,my_outline);
end loop;
end loop;
end if;
end process;
end architecture;