VHDL: Predicting how many bits an expression is made of

[J90]

Hi there,

Let's take the following example:

rom_addr := std_logic_vector(unsigned(ram_db)*((font_width*font_height)/8) + (unsigned(pix_x) + unsigned(pix_y)*font_width)/8);

Where:

signal ram_db: std_logic_vector(7 downto 0);
constant font_width: integer range integer'right downto 8 := 8;
constant font_height: integer range integer'right downto 8 := 8; 
variable pix_x, pix_y: std_logic_vector(4 downto 0);

I know the above expression results in a std_logic_vector of 16 elements. This after receiving a warning from the compiler for a size mismatch in the assignment.

Is there any way to predict the size in bits of the above std_logic_vector?


Thanks

 

[permute]

holy mother of f***.

Its like every dirty thing you can do has been done.

 

[J90]

Tell me more please!

By the way the synthesizer just instantiate some adders, multipliers and stuff for that expression (as I expected). What's wrong with it ?

 

[vipinlal]

You cant predict the number of bits in the result automatically.But you can simply calculate it.

In your case each of the below signal require the following number of bits:


ram_db - 8 bit.
font_height,font_width - 4 bit each
pix_x, pix_y - 5 bit each.

Now consider the expression:
ram_db*((font_width*font_height)/8) + (pix_x + pix_y*font_width)/8)

For multiplication the result width will be equal to sum of the number of bits in num1 and num2.
Analyzing that way, first term has 16(8+4+4) bit result and second term has 9(5+4) bits.
Now for addition the resultant width will be equal to the number of bits in the bigger number.
so the result comes to 16 bit in size.

--vipin
https://vhdlguru.blogspot.com/

 

[J90]

Thank you vipinlal! That was helpful, just what I was looking for


Still, I'd like to know what permute was talking about, maybe it's not the right way to accomplish such an operation ?

 

[vipinlal]

I will write down some points here:
1)You are doing a big calculation there in one single line.Break down it into a more readable format.
2)Why are declaring CONSTANT's in a complicated way?Just use this:
constant var_name : integer :=8;
The synthesis tool will trim the unused bits here(bits 31 downto 4).So leave such jobs to the synthesis tool and write the code more clearly.

this is all I have for now.Wait for permute to answer.

--vipin
https://vhdlguru.blogspot.com/

 

[J90]

1)You are doing a big calculation there in one single line.Break down it into a more readable format.

Yea, I sure would better brake it down.

2)Why are declaring CONSTANT's in a complicated way?Just use this:
constant var_name : integer :=8;

Well, to be honest that constant was born as a generic.
Not much time after I discovered the compiler does not like generics as arguments for case statements, because they're not locally static. As a consequence I chose to change it for a constant.
The "downto 8" means: hey future me, are you going to change that constant? Fair enough, but don't you set it lower than 8 or something bad will happen (i.e. the code does not support that constant to be lower than 8 ).
Yea, maybe a comment would have done the trick too

Wait for permute to answer.

Let's wait

 

[TrickyDicky]

The "downto 8" means: hey future me, are you going to change that constant? Fair enough, but don't you set it lower than 8 or something bad will happen (i.e. the code does not support that constant to be lower than 8 ).
Yea, maybe a comment would have done the trick too

You can use asserts to catch bad generic choices. and quartus at least will act on them properly (after a discussion on comp.lang.vhdl, most compilers just issue a warning).

assert (my_generic > 8) report "Generic has to be greater than 8" severity failure;

you can put this line of code inside your architecture.