Solved, I've reset Counter and StopCount in ModuleEN. Can you explain me why should I reset Counter and StopCount in process if I already assing them value 0 when I declare them?
I actually told you to add counter to the ModuleEN portion of the if in my previous post.
You're still using a gated clock. If the synthesis tool is good then it may be translating the gating signal into a clock enable, but my advice is don't force the tools to do those kinds of translations. Instead code the gated clock as an enable yourself.
Let me reiterate
avoid gated clocks in FPGA. Gated clocks in FPGAs are bad for the following reasons:
1. If you are using Xilinx there is a multiplexer for switching between two clocks, it can be used to gate a clock, but I'm pretty sure it should be instantiated. Drawback is that code is 100% non-portable.
2. Gated clocks need a "logic gate" i.e. a LUT to act as the gate. Drawback: local routing resources in an FPGA are usually bad for routing a clock if you expect to have a synchronous design, there are also many restrictions to routing LUT outputs to global clock resources and the inherent problem with the additional insertion delay on the clock.
3. Gated clocks may require special handling in the constraints to ensure they meet timing and don't produce glitches (this is the reason many FPGA synthesis tools default to converting gated clocks to enables).
Take a look at the synthesis messages and you'll probably see something like a warning telling you it's converting the gated clock to an enable. If there isn't then maybe your using a non Altera/Xilinx device that has some special resources to deal with clock gating.