# VHDL power sequencer

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#### Yaro

##### Newbie level 6
I'm trying to create a power sequencer in VHDL, this is my code:

Code:
library IEEE;

use IEEE.std_logic_1164.all;

entity PowerSeq is
port (
RESET : out std_logic;
POWER : out std_logic;
EN : out std_logic;
CLOCK : out std_logic;
SERIAL : out std_logic;
ModuleEN : in std_logic;
ModuleCLK : in std_logic
);
end PowerSeq;

architecture ArchiPowerSeq of PowerSeq is
signal counter :integer :=0;
signal StopCount :std_logic := '0';

begin
process(ModuleCLK)
begin
if (rising_edge(ModuleCLK) and StopCount = '0') then
if ModuleEN = '0' then
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
end if;
counter <= counter + 1;

-- 1ms = 250000
case counter is
when 2500000 =>
EN <= '1';
when 5000000 =>
POWER <= '0';
when 7500000 =>
CLOCK <= '1';
when 10000000 =>
RESET <= '1';
when 12500000=>
SERIAL <= '1';
StopCount <= '1';
when others =>

end case;
end if;
end process;

end ArchiPowerSeq;

I've an input clock of 250Mhz(just for example, I've also tryed lower as 50Mhz).

Simulating PowerSeq VHDL code works like expected, but when i Synthesize it and simulate Synthesized code in simulation tool I have correct EN input and Clock input but I have all X on outputs. Programming device my outputs are blocked with this values:

Code:
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
What is wrong with this code?

#### KlausST

##### Super Moderator
Staff member
Hi,

I´m not very familiar with VHDL code...

maybe:
if (rising_edge(ModuleCLK) and StopCount = '0') then

--> if (rising_edge(ModuleCLK) and (StopCount = '0')) then

Hope this helps...

Klaus

##### Super Moderator
Staff member
Maybe get rid of the gated clock altogether as a first step. That is a big no-no in FPGAs, especially if you would like to implement a design that works. StopCount should be implemented as an enable.

Also the if statement should have as the else clause the entire code from the counter assignment to the end of the case. I've always gone by the rule if you can't directly see the hardware described by the code, then you've probably written code that takes way too much effort for the synthesis tool to understand.

counter should probably be added to the if clause to ensure that the counter resets when the ModuleEN goes inactive. As currently coded if the ModuleEN goes 0 counter keeps going and when ModuleEN goes active the counter is at some arbitrary value.

Simulating PowerSeq VHDL code works like expected
I'm sure if I look at this code some more I'll find other issues. You did not do a thorough job of verifying the design in simulation. Unless what I've describe as the counter operation is what you expected.

#### Yaro

##### Newbie level 6
I've done some change to see if it was counter size problem, clock speed, counter running without EN(also added a library) and counter reset and I've tryed this code:

Code:
library IEEE;

use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity PowerSeq is
port (
RESET : out std_logic;
POWER : out std_logic;
EN : out std_logic;
CLOCK : out std_logic;
SERIAL : out std_logic;
ModuleEN : in std_logic;
ModuleCLK : in std_logic
);
end PowerSeq;

architecture ArchiPowerSeq of PowerSeq is
signal counter : std_logic_vector(3 downto 0) := "0000";
signal StopCount :std_logic := '0';

begin
process(ModuleCLK)
begin
if ModuleEN = '0' then
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
elsif (rising_edge(ModuleCLK) and StopCount = '0') then
counter <= counter + 1;

-- 1ms = 250000
case counter is
when "0001" =>
EN <= '1';
when "0010" =>
POWER <= '0';
when "0011" =>
CLOCK <= '1';
when "0100" =>
RESET <= '1';
when "0101"=>
SERIAL <= '1';
StopCount <= '1';
counter <= "0000";
when others =>
end case;

end if;
end process;

end ArchiPowerSeq;

Works in vhdl code simulation but when i synt it and simulate it doesn't work like expected, outputs starts with ModuleEN conditions and after some clock output go to X state.

- - - Updated - - -

Solved, I've reset Counter and StopCount in ModuleEN. Can you explain me why should I reset Counter and StopCount in process if I already assing them value 0 when I declare them?

#### FvM

##### Super Moderator
Staff member
The signal initializers should be translated to power on reset. There are several possibilities why this doesn't work in your simulation:

- Your PLD doesn't support power on reset of registers
- The PLD does support it, but the simulation libraries aren't aware of it
- The testbench signal sequence results in undefined state of the counter signal (e.g. involves undefined signals or timing violations)

In any case, you should provide proper reset for all design registers if possible. In case that you try to generate a kind of self-reset because no external reset signal is available, the respective logic circuit has to be designed with care.

##### Super Moderator
Staff member
Solved, I've reset Counter and StopCount in ModuleEN. Can you explain me why should I reset Counter and StopCount in process if I already assing them value 0 when I declare them?
I actually told you to add counter to the ModuleEN portion of the if in my previous post.

You're still using a gated clock. If the synthesis tool is good then it may be translating the gating signal into a clock enable, but my advice is don't force the tools to do those kinds of translations. Instead code the gated clock as an enable yourself.

Let me reiterate avoid gated clocks in FPGA. Gated clocks in FPGAs are bad for the following reasons:
1. If you are using Xilinx there is a multiplexer for switching between two clocks, it can be used to gate a clock, but I'm pretty sure it should be instantiated. Drawback is that code is 100% non-portable.
2. Gated clocks need a "logic gate" i.e. a LUT to act as the gate. Drawback: local routing resources in an FPGA are usually bad for routing a clock if you expect to have a synchronous design, there are also many restrictions to routing LUT outputs to global clock resources and the inherent problem with the additional insertion delay on the clock.
3. Gated clocks may require special handling in the constraints to ensure they meet timing and don't produce glitches (this is the reason many FPGA synthesis tools default to converting gated clocks to enables).

Take a look at the synthesis messages and you'll probably see something like a warning telling you it's converting the gated clock to an enable. If there isn't then maybe your using a non Altera/Xilinx device that has some special resources to deal with clock gating.

#### Yaro

##### Newbie level 6
In this case(updated code) I've used two gated clocks? First is StopCount and second is ModuleEN, right?

But how I can stop counting? For example if I use an integer, when I reach last case and I don't need to count further and counter reach it's maximum value, what happen?

Something like this, is ok to stop counter?

Code:
begin
process(ModuleCLK)
begin
if rising_edge(ModuleCLK) then
if ModuleEN = '0' then
RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';
elsif  StopCount = '1' then
counter <= "0000";
else
counter <= counter + 1;

case counter;
endif;

UPDATE

I've tryed the code, If I place ModuleEN inside "if rising_edge(ModuleCLK) then" but I get the previous error of X state of output pins. But I need to have in ModuleEN described output pin states until I enable module, where should I place it to avoid gated clock and make the code working?

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